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CY7S1049GE30-10VXIT PDF预览

CY7S1049GE30-10VXIT

更新时间: 2024-11-07 14:56:11
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
21页 553K
描述
Asynchronous SRAM

CY7S1049GE30-10VXIT 数据手册

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CY7S1049G  
CY7S1049GE  
4-Mbit (512K words × 8-bit) Static RAM  
with PowerSnooze™  
and Error Correcting Code (ECC)  
4-Mbit (512K words  
× 8-bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)  
ultra-low power Deep-Sleep mode[3]. With Deep-Sleep mode  
currents as low as 15 µA, the CY7S1049G/CY7S1049GE  
devices combine the best features of fast and low- power SRAMs  
in industry-standard package options. The device also features  
embedded ECC. logic which can detect and correct single-bit  
errors in the accessed location.  
Features  
High speed  
Access time (tAA) = 10 ns / 15 ns  
Ultra-low power Deep-Sleep (DS) current  
IDS = 15 µA  
Deep-Sleep input (DS) must be deasserted HIGH for normal  
operating mode.  
Low active and standby currents  
Active Current ICC = 38-mA typical  
Standby Current ISB2 = 6-mA typical  
To perform data writes, assert the Chip Enable (CE) and Write  
Enable (WE) inputs LOW, and provide the data and address on  
device data pins (I/O0 through I/O7) and address pins (A0  
through A18) respectively.  
Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,  
4.5 V to 5.5 V  
Embedded ECC for single-bit error correction[1, 2]  
To perform data reads, assert the Chip Enable (CE) and Output  
Enable (OE) inputs LOW and provide the required address on  
the address lines. Read data is accessible on the I/O lines (I/O0  
through I/O7).  
Error indication (ERR) pin to indicate 1-bit error detection and  
correction  
1.0-V data retention  
The device is placed in a low-power Deep-Sleep mode when the  
Deep-Sleep input (DS) is asserted LOW. In this state, the device  
is disabled for normal operation and is placed in a low power data  
retention mode. The device can be activated by deasserting the  
Deep-Sleep input (DS) to HIGH.  
TTL- compatible inputs and outputs  
Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)  
molded SOJ  
Functional Description  
The CY7S1049G/CY7S1049GE[1] is  
PowerSnooze™ static RAM organized as 512K words × 8 bits.  
This device features fast access times (10 ns) and a unique  
The CY7S1049G is available in 44-pin TSOP II, and 36-pin  
Molded SOJ (400 Mils).  
a
high-performance  
Product Portfolio  
Power Dissipation  
Operating ICC  
,
Speed  
(ns)  
Standby, ISB2  
Deep-Sleep  
current (µA)  
Product[4]  
Range  
VCC Range (V)  
(mA)  
(mA)  
f = fmax  
Typ [5] Max Typ [5] Max Typ [5] Max  
CY7S1049G(E)18 Industrial  
CY7S1049G(E)30  
1.65 V–2.2 V  
2.2 V–3.6 V  
4.5–5.5 V  
15  
10  
10  
40  
45  
45  
6
8
15  
38  
38  
CY7S1049G(E)  
Notes  
1. This device does not support automatic write back on error detection.  
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.  
3. Refer AN89371 for details on PowerSnooze™ feature.  
4. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 17 for details.  
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V  
CC  
CC  
CC  
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC  
CC  
A
Cypress Semiconductor Corporation  
Document Number: 001-95414 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 3, 2018  

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