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CY7C68000-56PVCT PDF预览

CY7C68000-56PVCT

更新时间： 2024-11-26 22:37:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 228K
描述
TX2 USB 2.0 UTMI Transceiver

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中文翻译

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CY7C68000-56PVCT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-56
针数：56Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.59差分输出：NO
驱动器位数：1输入特性：STANDARD
接口集成电路类型：LINE TRANSCEIVER接口标准：GENERAL PURPOSE
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm湿度敏感等级：1
功能数量：1端子数量：56
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：220认证状态：Not Qualified
最大接收延迟：接收器位数：1
座面最大高度：2.794 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5057 mm
Base Number Matches：1

CY7C68000-56PVCT 数据手册

 浏览型号CY7C68000-56PVCT的Datasheet PDF文件第2页浏览型号CY7C68000-56PVCT的Datasheet PDF文件第3页浏览型号CY7C68000-56PVCT的Datasheet PDF文件第4页浏览型号CY7C68000-56PVCT的Datasheet PDF文件第5页浏览型号CY7C68000-56PVCT的Datasheet PDF文件第6页浏览型号CY7C68000-56PVCT的Datasheet PDF文件第7页 
CY7C68000  
PRELIMINARY  
TX2™ USB 2.0 UTMI Transceiver  
• Synchronous field and EOP detection on receive pack-  
ets  
1.0  
EZ-USBTX2Features  
The Cypress EZ-USB TX2is a Universal Serial Bus (USB)  
specification revision 2.0 transceiver, serial/deserializer, to a  
parallel interface of either 16 bits at 30 MHz or eight bits at 60  
MHz. The TX2 provides a high-speed physical layer interface  
that operates at the maximum allowable USB 2.0 bandwidth.  
This allows the system designer to keep the complex high-  
speed analog USB components external to the digital ASIC  
which decreases development time and associated risk. A  
standard interface is provided that is USB 2.0-certified and is  
compliant with Transceiver Macrocell Interface (UTMI) speci-  
fication version 1.05 dated 3/29/01.  
• Synchronous field and EOP generation on transmit  
packets  
• Data and clock recovery from the USB serial stream  
• Bit stuffing/unstuffing; bit stuff error detection  
• Staging register to manage data rate variation due to  
bit stuffing/unstuffing  
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface  
• Ability to switch between FS and HS terminations and  
signaling  
• Supports detection of USB reset, suspend, and resume  
Two packages are defined for the family: 56-pin SSOP and 56-  
pin QFN.  
• Supports HS identification and detection as defined by  
the USB 2.0 Specification  
The function block diagram is shown in Figure 1-1.  
• Supports transmission of resume signaling  
• 3.3V operation  
• UTMI-compliant/USB-2.0-certified for device operation  
• Operates in both USB 2.0 high speed (HS), 480  
Mbits/second, and full speed (FS), 12 Mbits/second  
• Two package options—56-pin QFN, and 56-pin SSOP  
• All required terminations, including 1.5K-ohm pull-up  
on DPLUS, are internal to chip  
• Serial-to-parallel and parallel-to-serial conversions  
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-  
tional external data interface  
• Supports USB 2.0 test modes.  
CY7C68000  
20X  
PLL  
XTALIN/  
OUT  
UTMI CLK  
OSC  
PLL_480  
UTMI CLK  
Full-Speed Rx  
High-Speed Rx  
UTMI Rx Ctl  
Digital  
Rx  
UTMI Rx Data 8/16  
Fast  
Digital  
Rx  
Traffic  
Sync  
Elasticity  
Buffer  
USB  
BIDI Option  
Also  
USB  
2.0  
Fast  
Digital  
Tx  
XCVR  
High-Speed Tx  
Full-Speed Tx  
UTMI Rx Data 8/16  
UTMI Tx Ctl  
Digital  
Tx  
Figure 1-1. Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-08016 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 2, 2004  
1234567...14

中文翻译

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CY7C68000-56PVCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C68000-56PVXC CYPRESS

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