Datasheet > CY7C455-12JC

CY7C455-12JC

更新时间： 2024-11-20 04:45:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
23页	372K
描述
FIFO, 512X18, 9ns, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52

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中文翻译

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CY7C455-12JC 数据手册

CY7C455

CY7C456

CY7C457

512 x 18, 1K x 18, and 2K x 18 Cascadable

Clocked FIFOs with Programmable Flags

• Depth Expansion Capability

• 52-pin PLCC and 52-pin PQFP

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

Functional Description

• 512 x 18 (CY7C455)

The CY7C455, CY7C456, and CY7C457 are high-speed,

low-power, first-in first-out (FIFO) memories with clocked read

and write interfaces. All are 18 bits wide. The CY7C455 has a

512-word memory array, the CY7C456 has a 1,024-word

memory array, and the CY7C457 has a 2,048-word memory

array. The CY7C455, CY7C456, and CY7C457 can be cas-

caded to increase FIFO depth. Programmable features in-

clude Almost Full/Empty flags and generation/checking of par-

ity. These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition, multi-

processor interfaces, and communications buffering.

• 1,024 x 18 (CY7C456)

• 2,048 x 18 (CY7C457)

• 0.65 micron CMOS for optimum speed/power

• High-speed 83-MHz operation (12 ns read/write cycle

time)

• Low power — I_CC=90 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (CKW) and a write enable

pin (ENW).

• TTL compatible

• Retransmit function

• Parity generation/checking

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

0 – 17

LogicBlock Diagram

Pin Configurations

INPUT

PLCC

Top View

CKW

ENW

52 51 50 49 48 47

FLAG/PARITY

PROGRAM

PARITY

WRITE

CONTROL

XI 11

ENW 12

FLAG

LOGIC

E/F

CKW

FL/RT

7C455

7C456

7C457

PAFE/XO

RAM

ARRAY

512 x 18

1024 x 18

2048 x 18

E/F

CKR

38 ENR

37 OE

XO/PAFE

WRITE

POINTER

READ

POINTER

/PG2/PE2

RESET

LOGIC

21 22 23 24 25 26 27 28 29 30 31 32 33

FL/RT

EXPANSION

LOGIC

THREE–STATE

OUTPUT REGISTER

READ

CONTROL

RETRANSMIT

LOGIC

, Q /PG1/PE1

, Q17/PG2/PE2

c455-1

c455-2

0 –

CKR

ENR

9– 16

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06003 Rev. *A

Revised December 26, 2002

12 3 4 5 6 7...23

中文翻译

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与CY7C455-12JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C455-12JI	CYPRESS	获取价格	FIFO, 512X18, 9ns, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-12JIR	CYPRESS	获取价格	FIFO, 512X18, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-12JIT	CYPRESS	获取价格	FIFO, 512X18, 9ns, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-14JC	CYPRESS	获取价格	FIFO, 512X18, 10ns, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-14JCR	CYPRESS	获取价格	FIFO, 512X18, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-14JCT	CYPRESS	获取价格	FIFO, 512X18, 10ns, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-14JI	CYPRESS	获取价格	暂无描述
CY7C455-14JIR	CYPRESS	获取价格	FIFO, 512X18, Synchronous, CMOS, PQCC52, PLASTIC, LCC-52
CY7C455-14LMB	CYPRESS	获取价格	FIFO, 512X18, 14ns, Synchronous, CMOS, CQCC52, CERAMIC, LCC-52
CY7C455-14NI	ETC	获取价格	x18 Synchronous FIFO

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