Datasheet > CY7C4275

CY7C4275

更新时间： 2024-02-18 11:51:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
21页	283K
描述
32K/64Kx18 Deep Sync FIFOs

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中文翻译

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数据手册

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CY7C4275 数据手册

285

CY7C4275

CY7C4285

32K/64Kx18 Deep Sync FIFOs

Functional Description

Features

The CY7C4275/85 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can

be cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and commu-

nications buffering.

• High-speed, low-power, first-in first-out (FIFO)

memories

• 32K x 18 (CY7C4275)

• 64K x 18 (CY7C4285)

• 0.5 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power

— I_CC=50 mA

— I_SB= 2 mA

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

• Fully asynchronous and simultaneous read and write

operation

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-running read clock (RCLK) and a read

enable pin (REN). In addition, the CY7C4275/85 have an output

enable pin (OE). The read and write clocks may be tied together for

single-clock operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to 100

MHz are achievable.

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

• TTL compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Depth Expansion Capability

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V_SSand the FL pin of all the remaining devic-

• 68-pin PLCC and 64-pin 10x10 TQFP

• Pin-compatible density upgrade to CY7C42X5

families

• Pin-compatible density upgrade to

IDT72205/15/25/35/45

es should be tied to V_CC

0 –17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

RAM

ARRAY

PAE

PAF

SMODE

32Kx18

64Kx18

WRITE

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

0– 17

RXO

4275–1

RCLK

REN

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06008 Rev. *A

Revised December 26, 2002

12 3 4 5 6 7...21

中文翻译

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与CY7C4275相关器件

型号	品牌	获取价格	描述	数据表
CY7C4275-10ASC	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs
CY7C4275-10ASI	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs
CY7C4275-10JC	CYPRESS	获取价格	FIFO, 32KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275-10JCR	CYPRESS	获取价格	FIFO, 32KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275-10JCT	CYPRESS	获取价格	FIFO, 32KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275-10JI	CYPRESS	获取价格	暂无描述
CY7C4275-10JIR	CYPRESS	获取价格	FIFO, 32KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275-10JIT	CYPRESS	获取价格	FIFO, 32KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4275-15ASC	CYPRESS	获取价格	32K/64Kx18 Deep Sync FIFOs
CY7C4275-15ASI	CYPRESS	获取价格	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, TQFP-64

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