CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K
x 9 Synchronous FIFOs
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
• Space saving 32-pin 7 mm × 7 mm TQFP
Featuresb
• 32-pin PLCC
• High-speed, low-power, first-in, first-out (FIFO)
memories
• Available in Pb-Free Packages
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (ICC = 20 mA)
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max = 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width expansion capability
Pin Configuration
Logic Block Diagram
D
0− 8
PLCC
Top View
INPUT
REGISTER
4
3
2
1 323130
29
28
D
D
PAF
PAE
GND
REN1
RCLK
REN2
OE
RS
WEN1
1
5
6
7
8
9
0
27 WCLK
26
25
24
23
22
21
WCLKWEN1 WEN2/LD
WEN2/LD
V
CC
FLAG
PROGRAM
REGISTER
Q
Q
Q
Q
10
11
12
13
8
7
6
5
WRITE
CONTROL
14151617181920
EF
PAE
PAF
FF
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
WRITE
POINTER
READ
POINTER
8Kx 9
RESET
LOGIC
RS
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
OE
Q
0− 8
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 14, 2005
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