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CY7C425-15DMB PDF预览

CY7C425-15DMB

更新时间： 2024-11-27 05:09:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
22页 512K
描述
256/512/1K/2K/4K x 9 Asynchronous FIFO

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中文翻译

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CY7C425-15DMB 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：0.300 INCH, CERDIP-28针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.18
最长访问时间：15 ns其他特性：RETRANSMIT
最大时钟频率 (fCLK)：40 MHz周期时间：25 ns
JESD-30 代码：R-GDIP-T28JESD-609代码：e0
长度：37.0205 mm内存密度：9216 bit
内存集成电路类型：OTHER FIFO内存宽度：9
功能数量：1端子数量：28
字数：1024 words字数代码：1000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：1KX9
输出特性：3-STATE可输出：NO
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP28,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：5.08 mm最大待机电流：0.008 A
子类别：FIFOs最大压摆率：0.1 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

CY7C425-15DMB 数据手册

 浏览型号CY7C425-15DMB的Datasheet PDF文件第2页浏览型号CY7C425-15DMB的Datasheet PDF文件第3页浏览型号CY7C425-15DMB的Datasheet PDF文件第4页浏览型号CY7C425-15DMB的Datasheet PDF文件第5页浏览型号CY7C425-15DMB的Datasheet PDF文件第6页浏览型号CY7C425-15DMB的Datasheet PDF文件第7页 
19/21/25/29/  
CY7C419/21/25/29/33  
256/512/1K/2K/4K x 9 Asynchronous FIFO  
Each FIFO memory is organized such that the data is read in  
the same sequential order that it was written. Full and Empty  
Features  
• Asynchronous first-in first-out (FIFO) buffer memories  
• 256 x 9 (CY7C419)  
• 512 x 9 (CY7C421)  
• 1K x 9 (CY7C425)  
• 2K x 9 (CY7C429)  
flags are provided to prevent overrun and underrun. Three ad-  
ditional pins are also provided to facilitate unlimited expansion  
in width, depth, or both. The depth expansion technique steers  
the control signals from one device to another in parallel, thus  
eliminating the serial addition of propagation delays, so that  
throughput is not reduced. Data is steered in a similar manner.  
• 4K x 9 (CY7C433)  
• Dual-ported RAM cell  
• High-speed 50.0-MHz read/write independent of  
depth/width  
• Low operating power: ICC = 35 mA  
• Empty and Full flags (Half Full flag in standalone)  
• TTL compatible  
• Retransmit in standalone  
• Expandable in width  
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP  
The read and write operations may be asynchronous; each  
can occur at a rate of 50.0 MHz. The write operation occurs  
when the write (W) signal is LOW. Read occurs when read (R)  
goes LOW. The nine data outputs go to the high-impedance  
state when R is HIGH.  
A Half Full (HF) output flag is provided that is valid in the stan-  
dalone and width expansion configurations. In the depth ex-  
pansion configuration, this pin provides the expansion out  
(XO) information that is used to tell the next FIFO that it will be  
activated.  
In the standalone and width expansion configurations, a LOW  
on the retransmit (RT) input causes the FIFOs to retransmit  
the data. Read enable (R) and write enable (W) must both be  
HIGH during retransmit, and then R is used to access the data.  
• Pin compatible and functionally equivalent to IDT7200,  
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,  
AM7202, AM7203, and AM7204  
Functional Description  
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,  
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated  
using an advanced 0.65-micron P-well CMOS technology. In-  
put ESD protection is greater than 2000V and latch-up is pre-  
vented by careful layout and guard rings.  
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and  
CY7C432/3 are first-in first-out (FIFO) memories offered in  
600-mil wide and 300-mil wide packages. They are, respec-  
tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-06001 Rev. *A  
Revised December 30, 2002  
1234567...22

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CY7C425-15JCT CYPRESS

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CY7C425-15LMB CYPRESS

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CY7C425-15PC CYPRESS

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 		256/512/1K/2K/4K x 9 Asynchronous FIFO

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