Datasheet > 可编程逻辑 > 可编程逻辑器件> CY7C346B-25JCT

CY7C346B-25JCT

更新时间： 2024-10-05 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	426K
描述
OT PLD, 40ns, CMOS, PQCC84, PLASTIC, LCC-84

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技术参数
数据手册

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CY7C346B-25JCT 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	84
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	其他特性：	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
最大时钟频率：	62.5 MHz	JESD-30 代码：	S-PQCC-J84
长度：	29.3116 mm	专用输入次数：	19
I/O 线路数量：	48	端子数量：	84
最高工作温度：	70 °C	最低工作温度：
组织：	19 DEDICATED INPUTS, 48 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
可编程逻辑类型：	OT PLD	传播延迟：	40 ns
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	29.3116 mm
Base Number Matches：	1

CY7C346B-25JCT 数据手册

USEULTRA37000™FOR

ALL NEW DESIGNS

CY7C346B

128-Macrocell MAX^®EPLD

The 128 macrocells in the CY7C346B are divided into eight

LABs, 16 per LAB. There are 256 expander product terms, 32

per LAB, to be used and shared by the macrocells within each

LAB.

Features

• 128 macrocells in eight logic array blocks (LABs)

• 20 dedicated inputs, up to 64 bidirectional I/O pins

• Programmable interconnect array

Each LAB is interconnected through the programmable inter-

connect array, allowing all signals to be routed throughout the

chip.

• Advanced 0.65-micron CMOS technology to increase

performance

The speed and density of the CY7C346B allow it to be used in

a wide range of applications, from replacement of large

amounts of 7400-series TTL logic, to complex controllers and

multifunction chips. With greater than 25 times the functionality

of 20-pin PLDs, the CY7C346B allows the replacement of over

50 TTL CY7C346B. By replacing large amounts of logic, the

CY7C346B reduces board space, part count, and increases

system reliability.

• Available in 84-pin CLCC, PLCC, and 100-pin PGA,

PQFP

Functional Description

The CY7C346B is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX^®architecture is

100% user-configurable, allowing the device to accommodate

a variety of independent logic functions.

Logic Block Diagram

INPUT [59] (N4) . 36

INPUT [60] (M5) . 37

INPUT [61] (N5) . 38

INPUT [64] (N6) . 41

INPUT [65] (M7) . 42

INPUT [66] (L7) . 43

INPUT [67] (N7) . 44

INPUT [70] (L8) . 47

INPUT [71] (N9) . 48

INPUT [72] (M9) . 49

1 (C7) [16] INPUT/CLK

. 78 (A10) [9] .....

. 79 (B9) [10] .....

80 (A9) [11] .....

. 83 (A8) [14] .....

. 84 (B7) [15] .....

INPUT

(A7) [17] .....

(C6) [20] .....

(A5) [21] .....

(B5) [22] .....

SYSTEM CLOCK

LAB A

LAB H

MACROCELL 120

MACROCELL 119

MACROCELL 118

MACROCELL 117

MACROCELL 116

MACROCELL 115

MACROCELL 114

MACROCELL 113

MACROCELL

[100] (C13) NC

[99] (D12) NC

[98] (D13) 77

[97] (E12) 76

[96] (E13) 75

[95] (F11) 74

[92] (G13) 73

[91] (G11) 72

8 (B13) [1]

9 (C12) [2]

10 (A13) [3]

11 (B12) [4]

12 (A12) [5]

13 (11) [6]

NC (A11) [7]

NC (B10) [8]

MACROCELL 121–128

MACROCELL 9–16

LAB B

LAB G

MACROCELL 104

MACROCELL 103

MACROCELL 102

MACROCELL 101

MACROCELL 100

MACROCELL 99

MACROCELL 98

MACROCELL 97

MACROCELL 17

MACROCELL 18

MACROCELL 19

MACROCELL 20

MACROCELL 21

MACROCELL 22

MACROCELL 23

MACROCELL 24

14 (A4) [23]

15 (B4) [24]

16 (A3) [25]

17 (A2) [26]

18 (B3) [27]

21 (A1) [28]

NC (B2) [29]

NC (B1) [30]

[90] (G12) NC

[89] (H13) NC

[86] (J13) 71

[85] (J12) 70

[84] (K13) 69

[83] (K12) 68

[82] (L13) 67

[81] (L12) 64

MACROCELL 105–112

MACROCELL 25–32

LAB C

LAB F

MACROCELL 33

MACROCELL 34

MACROCELL 35

MACROCELL 36

MACROCELL 37

MACROCELL 38

MACROCELL 39

MACROCELL 40

22 (C2) [31]

25 (C1) [32]

26 (D2) [33]

27 (D1) [34]

28 (E2) [35]

29 (E1) [36]

NC (F1) [39]

NC (G2)[40]

[80] (M13) NC

[79] (M12) NC

[78] (N13) 63

[77] (M11) 60

[76] (N12) 59

[75] (N11) 58

[74] (M10) 57

[73] (N10) 56

MACROCELL 88

MACROCELL 87

MACROCELL 86

MACROCELL 85

MACROCELL 84

MACROCELL 83

MACROCELL 82

MACROCELL 81

MACROCELL 41–48

MACROCELL 86–96

LAB D

LAB E

MACROCELL 49

MACROCELL 50

MACROCELL 51

MACROCELL 52

MACROCELL 53

MACROCELL 54

MACROCELL 55

MACROCELL 56

[58] (M4) NC

[57] (N3) NC

[56] (M3) 55

[55] (N2) 54

[54] (M2) 53

[53] (N1) 52

[52] (L2) 51

[51] (M1) 50

MACROCELL 72

MACROCELL 71

MACROCELL 70

MACROCELL 69

MACROCELL 68

MACROCELL 67

MACROCELL 66

MACROCELL 65

30 (G3) [41]

31 (G1) [42]

32 (H3) [45]

33 (J1) [46]

34 (J2) [47]

35 (K1) [48]

NC (K2) [49]

NC (L1) [50]

MACROCELL 73–80

MACROCELL 57– 64

() – PERTAIN TO 100-PIN PGA PACKAGE

[ ] –PERTAIN TO 100-PIN PQFP PACKAGE

3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]

16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]

GND

Cypress Semiconductor Corporation

Document #: 38-03037 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised April 9, 2004

12 3 4 5 6 7...15

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与CY7C346B-25JCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C346B-25JI	ETC	获取价格
CY7C346B-25JIR	CYPRESS	获取价格	暂无描述
CY7C346B-25JIT	CYPRESS	获取价格	OT PLD, 40ns, CMOS, PQCC84, PLASTIC, LCC-84
CY7C346B-25NC	ETC	获取价格	UV-Erasable/OTP Complex PLD
CY7C346B-25NC/NI	CYPRESS	获取价格	128-Macrocell MAX㈢ EPLD
CY7C346B-25NCNI	CYPRESS	获取价格	128-Macrocell MAX EPLD
CY7C346B-25NI	ETC	获取价格
CY7C346B-25RC/RI	CYPRESS	获取价格	128-Macrocell MAX㈢ EPLD
CY7C346B-25RCRI	CYPRESS	获取价格	128-Macrocell MAX EPLD
CY7C346B-25RI	ETC	获取价格	UV-Erasable/OTP Complex PLD

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