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CY7C344B-15WMB PDF预览

CY7C344B-15WMB

更新时间: 2024-10-05 03:00:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
17页 296K
描述
32-Macrocell MAX㈢ EPLD

CY7C344B-15WMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:WDIP, DIP28,.3
针数:28Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.89其他特性:MACROCELLS INTERCONNECTED BY PIA; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
架构:PAL-TYPE最大时钟频率:40 MHz
JESD-30 代码:R-GDIP-T28JESD-609代码:e0
长度:37.0205 mm专用输入次数:7
I/O 线路数量:16输入次数:24
输出次数:16产品条款数:320
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C组织:7 DEDICATED INPUTS, 16 I/O
输出函数:MACROCELL封装主体材料:CERAMIC, GLASS-SEALED
封装代码:WDIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE, WINDOW
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
可编程逻辑类型:UV PLD传播延迟:30 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Programmable Logic Devices
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm

CY7C344B-15WMB 数据手册

 浏览型号CY7C344B-15WMB的Datasheet PDF文件第2页浏览型号CY7C344B-15WMB的Datasheet PDF文件第3页浏览型号CY7C344B-15WMB的Datasheet PDF文件第4页浏览型号CY7C344B-15WMB的Datasheet PDF文件第5页浏览型号CY7C344B-15WMB的Datasheet PDF文件第6页浏览型号CY7C344B-15WMB的Datasheet PDF文件第7页 
1CY7C344B  
fax id: 6101  
CY7C344  
CY7C344B  
32-Macrocell MAX® EPLD  
sents the densest EPLD of this size. Eight dedicated inputs  
and 16 bidirectional I/O pins communicate to one logic array  
block. In the CY7C344 LAB there are 32 macrocells and 64  
expander product terms. When an I/O macrocell is used as an  
input, two expanders are used to create an input path. Even if  
all of the I/O pins are driven by macrocell registers, there are  
still 16 “buried” registers available. All inputs, macrocells, and  
I/O pins are interconnected within the LAB.  
Features  
• High-performance, high-density replacement for TTL,  
74HC, and custom logic  
• 32 macrocells, 64 expander product terms in one LAB  
• 8 dedicated inputs, 16 I/O pins  
• 0.8-micron double-metal CMOS EPROM technology  
(CY7C344)  
The speed and density of the CY7C344/CY7C344B makes it  
a natural for all types of applications. With just this one device,  
the designer can implement complex state machines, regis-  
tered logic, and combinatorial “glue” logic, without using mul-  
tiple chips. This architectural flexibility allows the  
CY7C344/CY7C344B to replace multichip TTL solutions,  
whether they are synchronous, asynchronous, combinatorial,  
or all three.  
• Advanced 0.65-micron CMOS EPROM technology to  
increase performance (CY7C344B)  
• 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC  
package  
Functional Description  
Available in a 28-pin 300-mil DIP or windowed J-leaded ce-  
ramic chip carrier (HLCC), the CY7C344/CY7C344B repre-  
Logic Block Diagram[1]  
Pin Configurations  
HLCC  
15(22) INPUT  
15(23) INPUT  
INPUT  
1(8)  
Top View  
INPUT/CLK 2(9)  
27(6)  
28(7)  
INPUT  
INPUT  
INPUT  
INPUT  
13(20)  
14(21)  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
10  
11  
I/O  
I/O  
I/O  
INPUT  
INPUT  
INPUT  
INPUT/CLK  
I/O  
24  
23  
22  
21  
20  
19  
MACROCELL 2  
MACROCELL 1  
I/O 3(10)  
I/O 4(11)  
I/O 5(12)  
I/O 6(13)  
I/O 9(16)  
I/O 10(17)  
I/O 11(18)  
I/O 12(19)  
I/O 17(24)  
I/O 18(25)  
I/O 19(26)  
I/O 20(27)  
I/O 23(2)  
I/O 24(3)  
I/O 25(4)  
I/O 26(5)  
INPUT  
INPUT  
INPUT  
INPUT  
I/O  
MACROCELL 4  
MACROCELL 6  
MACROCELL 8  
MACROCELL 10  
MACROCELL 12  
MACROCELL 14  
MACROCELL 16  
MACROCELL 18  
MACROCELL 20  
MACROCELL 22  
MACROCELL 24  
MACROCELL 26  
MACROCELL 28  
MACROCELL 30  
MACROCELL 32  
MACROCELL 3  
MACROCELL 5  
MACROCELL 7  
MACROCELL 9  
MACROCELL 11  
MACROCELL 13  
MACROCELL 15  
MACROCELL 17  
MACROCELL 19  
MACROCELL 21  
MACROCELL 23  
MACROCELL 25  
MACROCELL 27  
MACROCELL 29  
MACROCELL 31  
G
L
I
O
O
B
A
L
I/O  
12 13 141516 1718  
C
O
N
T
C344–2  
CerDIP  
Top View  
B
U
S
R
O
L
INPUT  
INPUT  
INPUT  
I/O  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
INPUT/CLK  
I/O  
2
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
CC  
V
CC  
GND  
I/O  
GND  
I/O  
8
9
I/O  
I/O  
10  
11  
12  
13  
14  
I/O  
I/O  
INPUT  
I/O  
I/O  
INPUT  
C344–1  
32  
64 EXPANDER PRODUCT TERM ARRAY  
INPUT  
INPUT  
C344–3  
Selection Guide  
7C344–15  
7C344–20  
7C344–25  
7C344B–10  
7C344B–12  
12  
7C344B–15  
7C344B–20  
7C344B–25  
Maximum Access Time (ns)  
10  
15  
20  
25  
Maximum  
Operating  
Current (mA)  
Commercial  
Military  
Industrial  
Commercial  
Military  
200  
200  
220  
220  
150  
170  
170  
200  
200  
220  
220  
150  
170  
170  
200  
220  
220  
150  
170  
170  
220  
150  
Maximum Standby  
Current (mA)  
150  
Industrial  
170  
Shaded area contains preliminary information.  
Note:  
1. Numbers in () refer to J-leaded packages.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
January 1990 – Revised October 1995  

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