5秒后页面跳转
捷配首页

Datasheet > CY7C342B-20RMB
CY7C342B-20RMB PDF预览

CY7C342B-20RMB

更新时间： 2024-11-18 20:10:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟输入元件可编程逻辑
页数 文件大小 规格书
20页 324K
描述
UV PLD, 42ns, 128-Cell, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68

阅读下载

中文翻译

获取价格

CY7C342B-20RMB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：PGA包装说明：WINDOWED, CERAMIC, PGA-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.63其他特性：LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
最大时钟频率：40 MHz系统内可编程：NO
JESD-30 代码：S-CPGA-P68JESD-609代码：e0
JTAG BST：NO长度：27.9527 mm
专用输入次数：7I/O 线路数量：52
宏单元数：128端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
组织：7 DEDICATED INPUTS, 52 I/O输出函数：MACROCELL
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：WPGA
封装等效代码：PGA68,11X11封装形状：SQUARE
封装形式：GRID ARRAY, WINDOW峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V可编程逻辑类型：UV PLD
传播延迟：42 ns认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：5.08 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：27.9527 mmBase Number Matches：1

CY7C342B-20RMB 数据手册

 浏览型号CY7C342B-20RMB的Datasheet PDF文件第2页浏览型号CY7C342B-20RMB的Datasheet PDF文件第3页浏览型号CY7C342B-20RMB的Datasheet PDF文件第4页浏览型号CY7C342B-20RMB的Datasheet PDF文件第5页浏览型号CY7C342B-20RMB的Datasheet PDF文件第6页浏览型号CY7C342B-20RMB的Datasheet PDF文件第7页 
1CY7C342B  
fax id: 6107  
CY7C342B  
128-Macrocell MAX® EPLDs  
The 128 macrocells in the CY7C342B are divided into 8 Logic  
Array Blocks (LABs), 16 per LAB. There are 256 expander  
product terms, 32 per LAB, to be used and shared by the mac-  
rocells within each LAB.  
Features  
• 128 macrocells in 8 LABs  
• 8 dedicated inputs, 52 bidirectional I/O pins  
• Programmable interconnect array  
• Advanced 0.65-micron CMOS technology to increase  
performance  
• Available in 68-pin HLCC, PLCC, and PGA  
Each LAB is interconnected with a programmable interconnect  
array, allowing all signals to be routed throughout the chip.  
The speed and density of the CY7C342B allows it to be used in a  
wide range of applications, from replacement of large amounts of  
7400-series TTL logic, to complex controllers and multifunction  
chips. With greater than 25 times the functionality of 20-pin PLDs,  
theCY7C342B allows the replacement of over 50TTLdevices. By  
replacing large amounts of logic, the CY7C342B reduces board  
space, part count, and increases system reliability.  
Functional Description  
The CY7C342B is an Erasable Programmable Logic Device  
(EPLD) in which CMOS EPROM cells are used to configure  
logic functions within the device. The MAX architecture is  
100% user configurable, allowing the devices to accommodate  
a variety of independent logic functions.  
LogicBlock Diagram  
1 (B6) INPUT/CLK  
INPUT  
INPUT  
INPUT  
INPUT  
(A7) 68  
(A8) 66  
(L6) 36  
(K6) 35  
2 (A6)  
32 (L4)  
34 (L5)  
INPUT  
INPUT  
INPUT  
SYSTEM CLOCK  
LAB A  
LABH  
(B8) 65  
(A9) 64  
(B9) 63  
(A10) 62  
(B10) 61  
(B11) 60  
(C11) 59  
(C10) 58  
MACROCELL 1  
MACROCELL 2  
MACROCELL 3  
MACROCELL 4  
MACROCELL 5  
MACROCELL 6  
MACROCELL 7  
MACROCELL 8  
MACROCELL 120  
MACROCELL 119  
MACROCELL 118  
MACROCELL 117  
MACROCELL 116  
MACROCELL 115  
MACROCELL 114  
MACROCELL 113  
4 (A5)  
5 (B4)  
6 (A4)  
7 (B3)  
8 (A3)  
9 (A2)  
10 (B2)  
11 (B1)  
MACROCELL 9-16  
MACROCELL 121-128  
LAB B  
LABG  
12 (C2)  
13 (C1)  
14 (D2)  
15 (D1)  
17 (E1)  
(D11) 57  
(D10) 56  
(E11) 55  
(F11) 53  
(F10) 52  
MACROCELL 101  
MACROCELL 100  
MACROCELL 99  
MACROCELL 98  
MACROCELL 97  
MACROCELL 17  
MACROCELL 18  
MACROCELL 19  
MACROCELL 20  
MACROCELL 21  
MACROCELL 22-32  
MACROCELL 102-112  
P
I
A
LAB C  
LABF  
18 (F2)  
19 (F1)  
21 (G1)  
22 (H2)  
23 (H1)  
(G11) 51  
(H11) 49  
(H10) 48  
(J11) 47  
(J10) 46  
MACROCELL 33  
MACROCELL 34  
MACROCELL 35  
MACROCELL 36  
MACROCELL 37  
MACROCELL 85  
MACROCELL 84  
MACROCELL 83  
MACROCELL 82  
MACROCELL 81  
MACROCELL 38-48  
MACROCELL 86-96  
LAB D  
LABE  
MACROCELL 49  
MACROCELL 50  
MACROCELL 51  
MACROCELL 52  
MACROCELL 53  
MACROCELL 54  
MACROCELL 55  
MACROCELL 56  
(K11) 45  
(K10) 44  
(L10) 43  
(L9) 42  
(K9) 41  
(L8) 40  
(K8) 39  
(L7) 38  
MACROCELL 72  
MACROCELL 71  
MACROCELL 70  
MACROCELL 69  
MACROCELL 68  
MACROCELL 67  
MACROCELL 66  
MACROCELL 65  
24 (J2)  
25 (J1)  
26 (K1)  
27 (K2)  
28 (L2)  
29 (K3)  
30 (L3)  
31 (K4)  
MACROCELL 73-80  
MACROCELL 57-64  
() –PERTAIN TO 68-PIN PGA PACKAGE  
3, 20, 37, 54 (B5, G2, K7, E10)  
16, 33, 50, 67 (E2, K5, G10, B7)  
V
CC  
C342B-1  
GND  
MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
October 1989 – Revised October 1995  
1234567...20

中文翻译

下载PDF

与CY7C342B-20RMB相关器件

型号 品牌 获取价格 描述 数据表
CY7C342B-20TMB CYPRESS

获取价格

 		UV PLD, 42ns, 128-Cell, CMOS, CQFP68, WINDOWED, CERQUAD-68
CY7C342B-25HC CYPRESS

获取价格

 		128-Macrocell MAX EPLDs
CY7C342B-25HI CYPRESS

获取价格

 		128-Macrocell MAX EPLDs
CY7C342B-25HMB CYPRESS

获取价格

 		UV PLD, 51ns, 128-Cell, CMOS, CQCC68, WINDOWED, LCC-68
CY7C342B-25JC CYPRESS

获取价格

 		128-Macrocell MAX EPLDs
CY7C342B-25JCR CYPRESS

获取价格

 		OT PLD, 51ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C342B-25JI CYPRESS

获取价格

 		128-Macrocell MAX EPLDs
CY7C342B-25JIR CYPRESS

获取价格

 		OT PLD, 51ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C342B-25JIT CYPRESS

获取价格

 		OT PLD, 40ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C342B-25RC CYPRESS

获取价格

 		128-Macrocell MAX EPLDs

与CY7C342B-20RMB相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证