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CY7C341B-35JCR PDF预览

CY7C341B-35JCR

更新时间： 2024-11-17 13:07:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 335K
描述
OT PLD, 75ns, CMOS, PQCC84, PLASTIC, LCC-84

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中文翻译

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CY7C341B-35JCR 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：84
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82其他特性：LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
最大时钟频率：22.2 MHzJESD-30 代码：S-PQCC-J84
长度：29.3116 mm专用输入次数：7
I/O 线路数量：64端子数量：84
最高工作温度：70 °C最低工作温度：
组织：7 DEDICATED INPUTS, 64 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
可编程逻辑类型：OT PLD传播延迟：75 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：29.3116 mm
Base Number Matches：1

CY7C341B-35JCR 数据手册

 浏览型号CY7C341B-35JCR的Datasheet PDF文件第2页浏览型号CY7C341B-35JCR的Datasheet PDF文件第3页浏览型号CY7C341B-35JCR的Datasheet PDF文件第4页浏览型号CY7C341B-35JCR的Datasheet PDF文件第5页浏览型号CY7C341B-35JCR的Datasheet PDF文件第6页浏览型号CY7C341B-35JCR的Datasheet PDF文件第7页 
USE ULTRA37000™ FOR  
ALL NEW DESIGNS  
CY7C341B  
192-Macrocell MAX® EPLD  
macrocells within each LAB. Each LAB is interconnected with  
a programmable interconnect array, allowing all signals to be  
routed throughout the chip.  
Features  
• 192 macrocells in 12 logic array blocks (LABs)  
• Eight dedicated inputs, 64 bidirectional I/O pins  
The speed and density of the CY7C341B allows it to be used  
in a wide range of applications, from replacement of large  
amounts of 7400-series TTL logic, to complex controllers and  
multifunction chips. With greater than 37 times the functionality  
of 20-pin PLDs, the CY7C341B allows the replacement of over  
75 TTL devices. By replacing large amounts of logic, the  
CY7C341B reduces board space, part count, and increases  
system reliability.  
• Advanced 0.65-micron CMOS technology to increase  
performance  
• Programmable interconnect array  
• 384 expander product terms  
• Available in 84-pin HLCC, PLCC, and PGA packages  
Functional Description  
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8  
macrocells are connected to I/O pins and eight are buried,  
while for LABs B, C, D, E, H, I, J, and K, four macrocells are  
connected to I/O pins and 12 are buried. Moreover, in addition  
to the I/O and buried macrocells, there are 32 single product  
term logic expanders in each LAB. Their use greatly enhances  
the capability of the macrocells without increasing the number  
of product terms in each macrocell.  
The CY7C341B is an Erasable Programmable Logic Device  
(EPLD) in which CMOS EPROM cells are used to configure  
logic functions within the device. The MAX® architecture is  
100% user-configurable, allowing the devices to accom-  
modate a variety of independent logic functions.  
The 192 macrocells in the CY7C341B are divided into 12 Logic  
Array Blocks (LABs), 16 per LAB. There are 384 expander  
product terms, 32 per LAB, to be used and shared by the  
Selection Guide  
7C341B-25  
7C341B-35  
Unit  
Maximum Access Time  
25  
35  
ns  
Cypress Semiconductor Corporation  
Document #: 38-03016 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised April 22, 2004  
1234567...12

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CY7C341B-35RC/RI CYPRESS

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CY7C341B-35RI ETC

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CY7C341B-35RMB ETC

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CY7C342 CYPRESS

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CY7C342-25 CYPRESS

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