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CY7C271A

更新时间： 2024-02-29 20:06:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 开关电源开关可编程只读存储器
页数 文件大小 规格书
11页 174K
描述
32K x 8 Power Switched and Reprogrammable PROM

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CY7C271A 数据手册

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1CY7C271A  
CY7C271A  
32K x 8 Power Switched and  
Reprogrammable PROM  
automatically powers down into a low-power stand-by mode.  
The CY7C271A is packaged in the 300-mil slim package and  
is available in a cerDIP package equipped with an erasure  
window to provide for reprogrammability. When exposed to UV  
light, the PROM is erased and can be reprogrammed. The  
memory cells utilize proven EPROM floating gate technology  
and byte-wide intelligent programming algorithms.  
Features  
• CMOS for optimum speed/power  
• Windowed for reprogrammability  
• High speed  
— 25 ns (Commercial)  
• Low power  
The CY7C271A offers the advantages of lower power,  
superior performance, and programming yield. The EPROM  
cell requires only 12.5V for the super voltage, and low current  
requirements allow for gang programming. The EPROM cells  
allow each memory location to be tested 100% because each  
location is written into, erased, and repeatedly exercised prior  
to encapsulation. Each PROM is also tested for AC perfor-  
mance to guarantee that after customer programming, the  
product will meet DC and AC specification limits.  
— 275 mW (Commercial)  
• Super low standby power  
— Less than 85 mW when deselected  
• EPROM technology 100%programmable  
• Slim 300-mil package  
• Direct replacement for bipolar PROMs  
• Capable of withstanding >4001V static discharge  
Reading the 7C271A is accomplished by placing active LOW  
signals on CS1 and CE, and an active HIGH on CS2. The  
contents of the memory location addressed by the address  
lines (A0–A14) will become available on the output lines  
(O0–O7).  
Functional Description  
The CY7C271A is a high-performance 32,768-word by 8-bit  
CMOS PROM. When disabled (CE HIGH), the 7C271A  
Logic Block Diagram  
Pin Configurations  
DIP/Flatpack  
V
1
28  
A
9
A
8
A
7
CC  
O
7
O
6
O
5
A
10  
2
27  
26  
A
14  
A
11  
3
A
A
13  
A
4
A
12  
25  
24  
23  
22  
21  
6
12  
A
5
A
4
5
A
13  
256 x 1024  
PROGRAMABLE  
ARRAY  
X
8 x 1 OF 128  
MULTIPLEXER  
A
11  
10  
6
A
14  
ADDRESS  
A
A
3
CS  
1
7
A
A
2
8
CS  
2
9
A
A
9
20  
19  
18  
17  
16  
CE  
1
A
8
10  
11  
12  
13  
0
O
O
7
A
7
O
O
O
4
O
3
0
6
A
6
O
5
O
4
O
3
1
A
5
O
2
A
4
14  
GND  
15  
A
3
Y
A
2
ADDRESS  
O
O
2
PLCC  
Top View  
A
1
A
0
1
POWER-DOWN  
3
2 1 2827  
26  
4
E
CLR  
25  
24  
23  
22  
21  
20  
19  
A
5
4
A
3
6
7
8
9
10  
11  
E
A
S
O
0
2
CP  
NC  
O
A
1
A
CE  
0
NC  
O
7
CS  
1
O
6
0
CS  
2
12 131415161718  
Cypress Semiconductor Corporation  
Document #: 38-04013 Rev. *B  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 28, 2002  
1234567...11

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