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CY7C265-40PC PDF预览

CY7C265-40PC

更新时间： 2024-09-17 00:00:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路光电二极管输出元件可编程只读存储器OTP只读存储器
页数 文件大小 规格书
11页 316K
描述
8K x 8 Registered PROM

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中文翻译

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CY7C265-40PC 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：0.300 INCH, PLASTIC, MO-095, DIP-28针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.71
Is Samacsys：N最长访问时间：20 ns
其他特性：PROGRAMMABLE SYNCHRONOUS OR ASYNCHRONOUS OUTPUT ENABLEI/O 类型：COMMON
JESD-30 代码：R-PDIP-T28JESD-609代码：e0
长度：34.67 mm内存密度：65536 bit
内存集成电路类型：OTP ROM内存宽度：8
功能数量：1端子数量：28
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP28,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified座面最大高度：4.82 mm
最大待机电流：0.1 A子类别：OTP ROMs
最大压摆率：0.1 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

CY7C265-40PC 数据手册

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65  
CY7C265  
8K x 8 Registered PROM  
If the asynchronous enable (E) is being used, the outputs may  
be disabled at any time by switching the enable to a logic  
HIGH, and may be returned to the active state by switching the  
enable to a logic LOW.  
Features  
• CMOS for optimum speed/power  
• High speed (Commercial)  
— 15 ns address set-up  
If the synchronous enable (ES) is being used, the outputs will  
go to the OFF or high-impedance state upon the next positive  
clock edge after the synchronous enable input is switched to  
a HIGH level. If the synchronous enable pin is switched to a  
logic LOW, the subsequent positive clock edge will return the  
output to the active state. Following a positive clock edge, the  
address and synchronous enable inputs are free to change  
since no change in the output will occur until the next  
LOW-to-HIGH transition of the clock. This unique feature al-  
lows the CY7C265 decoders and sense amplifiers to access  
the next location while previously addressed data remains sta-  
ble on the outputs.  
— 12 ns clock to output  
• Low power  
— 660 mW (Commercial)  
• On-chip edge-triggered registers  
— Ideal for pipelined microprogrammed systems  
• EPROM technology  
— 100% programmable  
— Reprogrammable (CY7C265W)  
• 5V ±10% VCC, commercial and military  
• Capable of withstanding >2001V static discharge  
• Slim 28-pin, 300-mil plastic or hermetic DIP  
If the E/I pin is used for INIT (asynchronous), then the outputs  
are permanently enabled. The initialize function is useful  
during power-up and time-out sequences, and can facilitate  
implementation of other sophisticated functions such as a  
built-in “jump start” address. When activated, the initialize  
control input causes the contents of a user programmed  
8193rd 8-bit word to be loaded into the on-chip register. Each  
bit is programmable and the initialize function can be used to  
load any desired combination of 1’s and 0’s into the register.  
In the unprogrammed state, activating INIT will generate a  
register clear (all outputs LOW). If all the bits of the initialize  
word are programmed to be a 1, activating INIT performs a  
register preset (all outputs HIGH).  
Functional Description  
The CY7C265 is a 8192 x 8 registered PROM. It is organized  
as 8,192 words by 8 bits wide, and has a pipeline output  
register. In addition, the device features a programmable  
initialize byte that may be loaded into the pipeline register with  
the initialize signal. The programmable initialize byte is the  
8,193rd byte in the PROM and its value is programmed at the  
time of use.  
Packaged in 28 pins, the PROM has 13 address signals (A0  
through A12), 8 data out signals (O0 through O7), E/I (enable  
or initialize), and CLOCK.  
Applying a LOW to the INIT input causes an immediate load  
of the programmed initialize word into the pipeline register and  
onto the outputs. The INIT LOW disables clock and must  
return HIGH to enable clock independent of all other inputs,  
including the clock.  
CLOCK functions as a pipeline clock, loading the contents of  
the addressed memory location into the pipeline register on  
each rising edge. The data will appear on the outputs if they  
are enabled. One pin on the CY7C265 is programmed to  
perform either the enable or the initialize function.  
Cypress Semiconductor Corporation  
Document #: 38-04012 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised October 9, 2002  
1234567...11

中文翻译

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CY7C265-50DC ETC

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CY7C265-50DMB CYPRESS

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CY7C265-50JC CYPRESS

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CY7C265-50JCR CYPRESS

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 		OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C265-50JCT CYPRESS

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 		OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C265-50LC ETC

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 		x8 EPROM
CY7C265-50LMB ETC

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 		EPROM|8KX8|CMOS|LLCC|28PIN|CERAMIC
CY7C265-50PI CYPRESS

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 		OTP ROM, 8KX8, 25ns, CMOS, PDIP28, 0.300 INCH, SLIM, PLASTIC, DIP-28

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