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CY7C2570KV18-550BZC PDF预览

CY7C2570KV18-550BZC

更新时间: 2024-11-05 06:51:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
28页 817K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture

CY7C2570KV18-550BZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.26最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):550 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
长度:15 mm内存密度:75497472 bit
内存集成电路类型:DDR SRAM内存宽度:36
功能数量:1端子数量:165
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.38 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:0.97 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
Base Number Matches:1

CY7C2570KV18-550BZC 数据手册

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CY7C2566KV18, CY7C2577KV18  
CY7C2568KV18, CY7C2570KV18  
PRELIMINARY  
72-Mbit DDR-II+ SRAM 2-Word Burst  
Architecture (2.5 Cycle Read Latency) with ODT  
Features  
Configurations  
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)  
550 MHz clock for high bandwidth  
With Read Cycle Latency of 2.5 cycles:  
CY7C2566KV18 – 8M x 8  
CY7C2577KV18 – 8M x 9  
2-word burst for reducing address bus frequency  
CY7C2568KV18 – 4M x 18  
CY7C2570KV18 – 2M x 36  
Double Data Rate (DDR) interfaces  
(data transferred at 1100 MHz) at 550 MHz  
Available in 2.5 clock cycle latency  
Functional Description  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
The CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and  
CY7C2570KV18 are 1.8V Synchronous Pipelined SRAMs  
equipped with DDR-II+ architecture. The DDR-II+ consists of an  
SRAM core with advanced synchronous peripheral circuitry.  
Addresses for read and write are latched on alternate rising  
edges of the input (K) clock. Write data is registered on the rising  
edges of both K and K. Read data is driven on the rising edges  
of K and K. Each address location is associated with two 8-bit  
words (CY7C2566KV18), 9-bit words (CY7C2577KV18), 18-bit  
words (CY7C2568KV18), or 36-bit words (CY7C2570KV18) that  
burst sequentially into or out of the device.  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Data valid pin (QVLD) to indicate valid data on the output  
On-Die Termination (ODT) feature  
Supported for D[x:0], BWS[x:0], and K/K inputs  
Synchronous internally self-timed writes  
DDR-II+ operates with 2.5 cycle read latency when DOFF is  
asserted HIGH  
These devices have an On-Die Termination feature supported  
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate  
external termination resistors, reduce cost, reduce board area,  
and simplify board routing.  
Operates similar to DDR-I device with 1 cycle read latency  
when DOFF is asserted LOW  
[1]  
Asynchronous inputs include an output impedance matching  
input (ZQ). Synchronous data outputs (Q, sharing the same  
physical pins as the data inputs D) are tightly matched to the two  
output echo clocks CQ/CQ, eliminating the need for separately  
capturing data from each individual DDR SRAM in the system  
design.  
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD  
Supports both 1.5V and 1.8V IO supply  
HSTL inputs and variable drive HSTL output buffers  
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1 compatible test access port  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Phase Locked Loop (PLL) for accurate data placement  
Table 1. Selection Guide  
Description  
Maximum Operating Frequency  
Maximum Operating Current  
550 MHz  
500 MHz  
500  
450 MHz  
450  
400 MHz  
400  
Unit  
MHz  
mA  
550  
740  
740  
760  
970  
x8  
x9  
690  
630  
580  
690  
630  
580  
x18  
x36  
700  
650  
590  
890  
820  
750  
Note  
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V  
= 1.4V to V  
.
DD  
DDQ  
Cypress Semiconductor Corporation  
Document Number: 001-15889 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 24, 2009  
[+] Feedback  

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