CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
ADVANCE
INFORMATION
144-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
CY7C1610KV18 – 16M x 8
CY7C1625KV18 – 16M x 9
CY7C1612KV18 – 8M x 18
CY7C1614KV18 – 4M x 36
■ 333 MHz clock for high bandwidth
■ 2-word burst on all accesses
Functional Description
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 666 MHz) at 333 MHz
The CY7C1610KV18, CY7C1625KV18, CY7C1612KV18, and
CY7C1614KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
QDR-II architecture has separate data inputs and data outputs
to completely eliminate the need to turn around the data bus that
exists with common IO devices. Each port is accessed through
a common address bus. The read address is latched on the
rising edge of the K clock and the write address is latched on the
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
rising edge of the clock. Accesses to the QDR-II read and write
K
■ Separate port selects for depth expansion
■ Synchronous internally self timed writes
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with two
8-bit words (CY7C1610KV18), 9-bit words (CY7C1625KV18),
■ QDR™-II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
18-bit
words
(CY7C1612KV18),
or
36-bit
words
(CY7C1614KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of input clocks (K and K and C and C), memory
bandwidth is maximized while simplifying system design by
eliminating bus turn arounds.
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen
DOFF is asserted LOW
■ Available in ×8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V(±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
Port selects for each port enable depth expansion. Port selects
allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Selection Guide
Parameter
333 MHz
333
300 MHz
300
250 MHz
250
200 MHz
200
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
x8/x9
x18
850
780
680
580
870
810
700
590
x36
1060
980
850
710
Cypress Semiconductor Corporation
Document #: 001-16238 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 21, 2007
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