Datasheet > 存储 > SRAM> CY7C1566V18-400BZC

CY7C1566V18-400BZC

更新时间： 2024-11-19 05:09:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
28页	665K
描述
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1566V18-400BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.45
Is Samacsys：	N	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	400 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	67108864 bit	内存集成电路类型：	DDR SRAM
内存宽度：	8	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	1.4 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

CY7C1566V18-400BZC 数据手册

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第2页

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第3页

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第4页

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第5页

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第6页

浏览型号CY7C1566V18-400BZC的Datasheet PDF文件第7页

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 400 MHz clock for high bandwidth

The CY7C1566V18, CY7C1577V18, CY7C1568V18, and

CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit

words (CY7C1568V18), or 36-bit words (CY7C1570V18) that

burst sequentially into or out of the device.

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

Asynchronous inputs include an output impedance matching

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1566V18 – 8M x 8

CY7C1577V18 – 8M x 9

CY7C1568V18 – 4M x 18

CY7C1570V18 – 2M x 36

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

400 MHz

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

400

1400

1300

1200

1100

x18

x36

1100

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06551 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 11, 2008

[+] Feedback

12 3 4 5 6 7...28

中文翻译

下载PDF

与CY7C1566V18-400BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1566V18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1566V18-400BZXI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1568KV18	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1568KV18-400BZC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1568KV18-400BZC	INFINEON	获取价格	DDR-II+ CIO
CY7C1568KV18-400BZI	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1568KV18-400BZXC	CYPRESS	获取价格	72-Mbit DDR-II+ SRAM 2-Word Burst Architecture
CY7C1568KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1568KV18-400BZXCT	CYPRESS	获取价格	Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165,

与CY7C1566V18-400BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1566V18-400BZC

CY7C1566V18-400BZC 技术参数

CY7C1566V18-400BZC 数据手册

与CY7C1566V18-400BZC相关器件

与CY7C1566V18-400BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1566V18-400BZC

CY7C1566V18-400BZC 技术参数

CY7C1566V18-400BZC 数据手册

与CY7C1566V18-400BZC相关器件

与CY7C1566V18-400BZC相关文章

您还可以找

您在本页遇到什么问题？