Datasheet > 存储 > SRAM> CY7C1529V18-300BZI

CY7C1529V18-300BZI

更新时间： 2024-11-20 05:19:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	446K
描述
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1522V18

CY7C1529V18

CY7C1523V18

CY7C1524V18

72-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

Features

Functional Description

• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

• 300-MHz clock for high bandwidth

The CY7C1522V18, CY7C1529V18, CY7C1523V18,

CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II SIO (Double Data Rate Separate I/O)

architecture. The DDR-II SIO consists of two separate ports to

access the memory array. The Read port has dedicated Data

outputs and the Write port has dedicated Data inputs to

completely eliminate the need to “turn around’ the data bus

required with common I/O devices. Access to each port is

accomplished using a common address bus. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with two 8-bit

words in the case of CY7C1522V18, two 9-bit words in the

case of CY7C1529V18, two 18-bit words in the case of

CY7C1523V18, and two 36-bit words in the case of

CY7C1524V18, that burst sequentially into or out of the

device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to

the two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SIO

SRAM in the system design. Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

• Available in 165-ballFBGA package (15 x 17 x 1.4 mm )

• Offered in lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry

Configuration

CY7C1522V18 – 8M x 8

CY7C1529V18 – 8M x 9

CY7C1523V18 – 4M x18

CY7C1524V18 – 2M x 36

Selection Guide

300 MHz

300

278 MHz

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

278

860

900

800

700

650

Cypress Semiconductor Corporation

Document #: 38-05564 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 1, 2006

12 3 4 5 6 7...28

中文翻译

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与CY7C1529V18-300BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1529V18-300BZXC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-300BZXI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C152AV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C152V18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1541KV18	CYPRESS	获取价格	72-Mbit QDRÂ®II SRAM 4-Word BurstArchitecture
CY7C1541V18	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1541V18_08	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1541V18-300BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1541V18-300BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1541V18-300BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu

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