Datasheet > CY7C1529KV18-333BZXI

CY7C1529KV18-333BZXI

更新时间： 2024-11-21 09:39:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器
页数	文件大小	规格书
32页	883K
描述
DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

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CY7C1522KV18, CY7C1529KV18

CY7C1523KV18, CY7C1524KV18

72-Mbit DDR II SIO SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 333 MHz Clock for High Bandwidth

The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and

CY7C1524KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with DDR II SIO (Double Data Rate Separate I/O)

architecture. The DDR II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR

II SIO has separate data inputs and data outputs to completely

eliminate the need to “turnaround” the data bus required with

common I/O devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1522KV18, two 9-bit words in the case of

CY7C1529KV18, two 18-bit words in the case of

CY7C1523KV18, and two 36-bit words in the case of

CY7C1524KV18 that burst sequentially into or out of the device.

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous Internally Self timed Writes

■ DDR II operates with 1.5 Cycle Read Latency when DOFF is

asserted HIGH

■ Operates similar to DDR-I Device with 1 Cycle Read Latency

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from each individual DDR II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

when DOFF is asserted LOW

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable Drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V_DD

❐ Supports both 1.5V and 1.8V IO supply

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Phase Locked Loop (PLL) for accurate Data Placement

Configurations

CY7C1522KV18 – 8M x 8

CY7C1529KV18 – 8M x 9

CY7C1523KV18 – 4M x 18

CY7C1524KV18 – 2M x 36

Table 1. Selection Guide

Description

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

510

480

420

370

340

510

480

420

370

340

x18

x36

520

490

430

380

340

640

600

530

450

400

Cypress Semiconductor Corporation

Document Number: 001-00438 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 29, 2010

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与CY7C1529KV18-333BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1529V18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1529V18-167BZC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-167BZI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-167BZXC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-167BZXI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-200BZC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-200BZI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-200BZXC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-200BZXI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529V18-250BZC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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