Datasheet > 存储 > SRAM> CY7C1529AV18-300BZC

CY7C1529AV18-300BZC

更新时间： 2024-11-20 05:19:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器双倍数据速率
页数	文件大小	规格书
28页	1160K
描述
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1529AV18-300BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	9	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX9
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.4 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.9 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

CY7C1529AV18-300BZC 数据手册

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CY7C1522AV18

CY7C1529AV18

CY7C1523AV18

CY7C1524AV18

PRELIMINARY

72-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

Features

Functional Description

• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

• 300-MHz clock for high bandwidth

The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18 and

CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II SIO (Double Data Rate Separate I/O)

architecture. The DDR-II SIO consists of two separate ports to

access the memory array. The Read port has dedicated Data

outputs and the Write port has dedicated Data inputs to

completely eliminate the need to “turn around’ the data bus

required with common I/O devices. Access to each port is

accomplished using a common address bus. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with two 8-bit

words in the case of CY7C1522AV18, two 9-bit words in the

case of CY7C1529AV18, two 18-bit words in the case of

CY7C1523AV18, and two 36-bit words in the case of

CY7C1524AV18, that burst sequentially into or out of the

device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• DDR-II operates with 1.5 cycle read latency when DLL

is enabled

• Operates like a DDR I device with 1 cycle read latency

in DLL off mode

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to

the two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SIO

SRAM in the system design. Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• Delay Lock Loop (DLL) for accurate data placement

Configuration

CY7C1522AV18 – 8M x 8

CY7C1529AV18 – 8M x 9

CY7C1523AV18 – 4M x 18

CY7C1524AV18 – 2M x 36

Cypress Semiconductor Corporation

Document #: 001-06981 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 20, 2006

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与CY7C1529AV18-300BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1529AV18-300BZI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529AV18-300BZXC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529AV18-300BZXI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-250BZC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-250BZI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-250BZXC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-250BZXI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-300BZC	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1529JV18-300BZI	CYPRESS	获取价格	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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