Datasheet > 存储 > SRAM> CY7C1518KV18-200BZXC

CY7C1518KV18-200BZXC

更新时间： 2024-11-27 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
30页	1188K
描述
72-Mbit DDR-II SRAM 2-Word Burst Architecture

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技术参数
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CY7C1518KV18-200BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.76	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.38 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	13 mm
Base Number Matches：	1

CY7C1518KV18-200BZXC 数据手册

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CY7C1516KV18, CY7C1527KV18

CY7C1518KV18, CY7C1520KV18

72-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 72-Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 333 MHz Clock for High Bandwidth

The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and

CY7C1520KV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1516KV18

and two 9-bit words in the case of CY7C1527KV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1516KV18 and

CY7C1527KV18. On CY7C1518KV18 and CY7C1520KV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518KV18 and two 36-bit words in the case of

CY7C1520KV18 sequentially into or out of the device.

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous Internally Self-timed Writes

■ DDR-II operates with 1.5 Cycle Read Latency when DOFF is

asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to DDR-I Device with 1 Cycle Read Latency

when DOFF is asserted LOW

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable Drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V_DD

❐ Supports both 1.5V and 1.8V IO supply

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Configurations

CY7C1516KV18 – 8M x 8

CY7C1527KV18 – 8M x 9

CY7C1518KV18 – 4M x 18

CY7C1520KV18 – 2M x 36

Table 1. Selection Guide

Description

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

510

480

420

370

340

510

480

420

370

340

x18

x36

520

490

430

380

340

640

600

530

450

400

Cypress Semiconductor Corporation

Document Number: 001-00437 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 30, 2009

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与CY7C1518KV18-200BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1518KV18-200BZXI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZI	INFINEON	获取价格	DDR-II CIO
CY7C1518KV18-250BZXC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZXI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZXI	INFINEON	获取价格	DDR-II CIO
CY7C1518KV18-300BZC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZXC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture

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