1CY7C1512
PRELIMINARY
CY7C1512
64K x 8 Static RAM
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Features
• High speed
— t = 15 ns
Writing to the device is accomplished by taking chip enable
AA
one (CE ) and write enable (WE) inputs LOW and chip enable
• CMOS for optimum speed/power
• Low active power
1
two (CE ) input HIGH. Data on the eight I/O pins (I/O through
2
0
I/O ) is then written into the location specified on the address
7
— 770 mW
pins (A through A ).
0
15
• Low standby power
Reading from the device is accomplished by taking chip en-
— 28 mW
able one (CE ) and output enable (OE) LOW while forcing
1
write enable (WE) and chip enable two (CE ) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
2
• Easy memory expansion with CE , CE , and OE options
1
2
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
Functional Description
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE ), an active
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
1
HIGH chip enable (CE ), an active LOW output enable (OE),
2
Logic Block Diagram
Pin Configurations
SOIC
Top View
V
NC
NC
32
31
30
1
CC
A
15
2
3
A
14
CE
2
A
4
WE
12
29
28
5
A
A
A
A
13
A
8
A
7
27
26
6
6
5
7
9
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
4
11
OE
A
A
10
I/O
2
0
A
1
CE
I/O
I/O
1
INPUT BUFFER
A
7
6
0
I/O
I/O
I/O
I/O
I/O
0
1
2
1
20
19
A
0
A
1
I/O
5
14
15
16
I/O
I/O
18
17
4
3
2
A
GND
2
1512-2
OE
A
3
4
A
A
A
A
1
2
I/O
I/O
I/O
32
31
11
3
4
5
64K x 8
ARRAY
A
A
9
8
5
6
10
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
A
1
A
I/O
7
13
A
7
WE
CE
I/O
I/O
6
5
2
A
TSOP I
15
I/O
I/O
4
3
Top View
V
CC
NC
NC
9
GND
(not to scale)
I/O
I/O
6
7
10
11
12
13
14
15
16
2
POWER
DOWN
COLUMN
DECODER
I/O
1
A
14
CE
1
A
I/O
12
0
CE
2
I/O
A
A
6
A
A
A
0
7
WE
A
1
A
2
5
4
A
OE
3
1512-1
Selection Guide
7C1512-15
7C1512-20
7C1512-25
7C1512-35
7C1512-70
Maximum Access Time (ns)
15
20
25
35
70
Maximum Operating
Current (mA)
Commercial
Commercial
140
130
120
110
110
Maximum CMOS
5
5
5
5
5
Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
June 1996 – Revised October 1996
•
408-943-2600