Datasheet > CY7C1510V18_06

CY7C1510V18_06

更新时间： 2024-11-27 05:19:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	489K
描述
72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1510V18_06 数据手册

CY7C1510V18

CY7C1525V18

CY7C1512V18

CY7C1514V18

72-Mbit QDR-II™ SRAM 2-Word Burst

Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

• 250-MHz clock for high bandwidth

• 2-Word Burst on all accesses

The CY7C1510V18, CY7C1525V18, CY7C1512V18, and

CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

the rising edge of the clock. Accesses to the QDR-II Read

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1510V18) or 9-bit words (CY7C1525V18) or 18-bit

words (CY7C1512V18) or 36-bit words (CY7C1514V18) that

burst sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising edge of

both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

• Core V_DD= 1.8V (±0.1V); I/O V_DDQ= 1.4V to V_DD

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in lead-free and non-lead free packages

• Variable drive HSTL output buffers

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1510V18 – 8M x 8

CY7C1525V18 – 8M x 9

CY7C1512V18 – 4M x 18

CY7C1514V18 – 2M x 36

Selection Guide

250 MHz

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

250

950

850

800

Cypress Semiconductor Corporation

Document #: 38-05489 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 31, 2006

[+] Feedback

12 3 4 5 6 7...27

中文翻译

下载PDF

与CY7C1510V18_06相关器件

型号	品牌	获取价格	描述	数据表
CY7C1510V18_09	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18-167BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-167BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-167BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-167BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-200BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-200BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-200BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-200BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510V18-250BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

与CY7C1510V18_06相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

34
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

63
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

60

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1510V18_06

CY7C1510V18_06 数据手册

与CY7C1510V18_06相关器件

与CY7C1510V18_06相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1510V18_06

CY7C1510V18_06 数据手册

与CY7C1510V18_06相关器件

与CY7C1510V18_06相关文章

您还可以找

您在本页遇到什么问题？