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CY7C1482BV33-250AXI PDF预览

CY7C1482BV33-250AXI

更新时间： 2024-11-08 12:19:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
34页 974K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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中文翻译

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CY7C1482BV33-250AXI 技术参数

是否Rohs认证： 符合生命周期：Active
Reach Compliance Code：compliant风险等级：5.63
最长访问时间：3 ns最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e4内存密度：75497472 bit
内存集成电路类型：STANDARD SRAM内存宽度：18
湿度敏感等级：3端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.5 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40Base Number Matches：1

CY7C1482BV33-250AXI 数据手册

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CY7C1480BV33  
CY7C1482BV33, CY7C1486BV33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Features  
Functional Description  
■ Supports bus operation up to 250 MHz  
■ Available speed grades are 250, 200, and 167 MHz  
■ Registered inputs and outputs for pipelined operation  
■ 3.3V core power supply  
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33  
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a 2-bit counter  
for internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE1), depth-expansion  
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWX, and BWE), and Global  
Write (GW). Asynchronous inputs include the Output Enable  
(OE) and the ZZ pin.  
■ 2.5V/3.3V IO operation  
■ Fast clock-to-output times  
❐ 3.0 ns (for 250 MHz device)  
■ Provide high performance 3-1-1-1 access rate  
Addresses and chip enables are registered at the rising edge of  
the clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent burst  
addresses may be internally generated as controlled by the  
Advance pin (ADV).  
■ User selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see sections Pin Definitions on page 7 and Truth  
Table on page 10 for further details). Write cycles can be one to  
two or four bytes wide as controlled by the byte write control  
inputs. GW when active LOW causes all bytes to be written.  
■ Asynchronous output enable  
■ Single cycle chip deselect  
■ CY7C1480BV33, CY7C1482BV33 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non Pb-free 165-ball FBGA package. CY7C1486BV33  
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33  
available in Pb-free and non-Pb-free 209-ball FBGA package  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ “ZZ” Sleep Mode option  
operates from a +3.3V core power supply while all outputs may  
operate with either a +2.5 or +3.3V supply. All inputs and outputs  
are JEDEC standard JESD8-5 compatible. For best practices  
recommendations, refer to the Cypress application note AN1064  
“SRAM System Guidelines”.  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Operating Current  
Maximum CMOS Standby Current  
500  
500  
450  
mA  
mA  
120  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15145 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 05, 2008  
[+] Feedback  
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