5秒后页面跳转
捷配首页

Datasheet > CY7C1482BV33-167AXC
CY7C1482BV33-167AXC PDF预览

CY7C1482BV33-167AXC

更新时间： 2024-11-07 12:19:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
34页 974K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

阅读下载

中文翻译

获取价格

CY7C1482BV33-167AXC 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：compliant
风险等级：5.64最长访问时间：3.4 ns
最大时钟频率 (fCLK)：167 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e4
内存密度：75497472 bit内存集成电路类型：STANDARD SRAM
内存宽度：18湿度敏感等级：3
端子数量：100字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.45 mA
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40

CY7C1482BV33-167AXC 数据手册

 浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第2页浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第3页浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第4页浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第5页浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第6页浏览型号CY7C1482BV33-167AXC的Datasheet PDF文件第7页 
CY7C1480BV33  
CY7C1482BV33, CY7C1486BV33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Features  
Functional Description  
■ Supports bus operation up to 250 MHz  
■ Available speed grades are 250, 200, and 167 MHz  
■ Registered inputs and outputs for pipelined operation  
■ 3.3V core power supply  
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33  
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a 2-bit counter  
for internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE1), depth-expansion  
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWX, and BWE), and Global  
Write (GW). Asynchronous inputs include the Output Enable  
(OE) and the ZZ pin.  
■ 2.5V/3.3V IO operation  
■ Fast clock-to-output times  
❐ 3.0 ns (for 250 MHz device)  
■ Provide high performance 3-1-1-1 access rate  
Addresses and chip enables are registered at the rising edge of  
the clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent burst  
addresses may be internally generated as controlled by the  
Advance pin (ADV).  
■ User selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see sections Pin Definitions on page 7 and Truth  
Table on page 10 for further details). Write cycles can be one to  
two or four bytes wide as controlled by the byte write control  
inputs. GW when active LOW causes all bytes to be written.  
■ Asynchronous output enable  
■ Single cycle chip deselect  
■ CY7C1480BV33, CY7C1482BV33 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non Pb-free 165-ball FBGA package. CY7C1486BV33  
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33  
available in Pb-free and non-Pb-free 209-ball FBGA package  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ “ZZ” Sleep Mode option  
operates from a +3.3V core power supply while all outputs may  
operate with either a +2.5 or +3.3V supply. All inputs and outputs  
are JEDEC standard JESD8-5 compatible. For best practices  
recommendations, refer to the Cypress application note AN1064  
“SRAM System Guidelines”.  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Operating Current  
Maximum CMOS Standby Current  
500  
500  
450  
mA  
mA  
120  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15145 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 05, 2008  
[+] Feedback  
1234567...34

中文翻译

下载PDF

与CY7C1482BV33-167AXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1482BV33-167AXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-167BZC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-167BZI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-167BZXC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-167BZXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-200AXC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-200AXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-200BZC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482BV33-200BZI CYPRESS

获取价格

 		72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
CY7C1482BV33-200BZI INFINEON

获取价格

 		Synchronous SRAM

与CY7C1482BV33-167AXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证