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CY7C1480V33_13 PDF预览

CY7C1480V33_13

更新时间: 2024-09-18 12:27:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
25页 479K
描述
72-Mbit (2 M x 36) Pipelined Sync SRAM

CY7C1480V33_13 数据手册

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CY7C1480V33  
72-Mbit (2 M × 36) Pipelined Sync SRAM  
72-Mbit (2  
M × 36) Pipelined Sync SRAM  
Features  
Functional Description  
Supports bus operation up to 200 MHz  
Available speed grades are 200 and 167 MHz  
Registered inputs and outputs for pipelined operation  
3.3 V core power supply  
The CY7C1480V33 SRAM integrates 2 M × 36 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit counter  
for internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE1), depth-expansion  
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWX, and BWE), and Global  
Write (GW). Asynchronous inputs include the Output Enable  
(OE) and the ZZ pin.  
2.5 V/3.3 V I/O operation  
Fast clock-to-output times  
3.0 ns (for 200 MHz device)  
Addresses and chip enables are registered at the rising edge of  
the clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
Provide high performance 3-1-1-1 access rate  
User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
Separate processor and controller address strobes  
Synchronous self timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see "Pin Definitions" on page 5 and "Truth Table" on  
page 8 for further details). Write cycles can be one to two or four  
bytes wide as controlled by the byte write control inputs. GW  
when active LOW causes all bytes to be written.  
Asynchronous output enable  
Single cycle chip deselect  
CY7C1480V33 available in JEDEC-standard Pb-free 100-pin  
The CY7C1480V33 operates from a +3.3 V core power supply  
while all outputs may operate with either a +2.5 or +3.3 V supply.  
All inputs and outputs are JEDEC standard JESD8-5 compatible.  
TQFP package  
IEEE 1149.1 JTAG-Compatible Boundary Scan  
“ZZ” Sleep Mode option  
Selection Guide  
Description  
Maximum Access Time  
200 MHz  
3.0  
167 MHz Unit  
3.4  
450  
120  
ns  
Maximum Operating Current  
500  
mA  
mA  
Maximum CMOS Standby Current  
120  
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05283 Rev. *N  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 19, 2013  

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