Datasheet > 存储 > SRAM> CY7C1480V33-200BZXI

CY7C1480V33-200BZXI

更新时间： 2024-11-29 05:19:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	1290K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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CY7C1480V33

CY7C1482V33

CY7C1486V33

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM

integrates 2M x 36/4M x 18/1M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_X,

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

— 3.0 ns (for 250 MHz device)

• Provide high performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

Addresses and chip enables are registered at the rising edge

of the clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• Single cycle chip deselect

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see “Pin Definitions” on page 7 and “Truth Table”

on page 10 for further details). Write cycles can be one to two

or four bytes wide as controlled by the byte write control inputs.

GW when active LOW causes all bytes to be written.

• CY7C1480V33, CY7C1482V33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1486V33

available in Pb-free and non-Pb-free 209-ball FBGA

package

The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates

from a +3.3V core power supply while all outputs may operate

with either a +2.5 or +3.3V supply. All inputs and outputs are

JEDEC standard JESD8-5 compatible.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

Selection Guide

250 MHz

3.0

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

500

450

120

Note

1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 38-05283 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 23, 2007

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与CY7C1480V33-200BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1480V33-250AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33-250AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33-250BGC	CYPRESS	获取价格	Cache SRAM, 2MX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1480V33-250BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33-250BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1481BV25_13	CYPRESS	获取价格	72-Mbit (2 M x 36) Flow-Through SRAM
CY7C1481BV25-133AXI	CYPRESS	获取价格	72-Mbit (2 M x 36) Flow-Through SRAM
CY7C1481BV33	CYPRESS	获取价格	72-Mbit (2 M Ã 36) Flow-Through SRAM

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