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CY7C148

更新时间： 2024-11-26 06:51:43
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赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 214K
描述
1Kx4 Static RAM

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CY7C148 数据手册

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49  
CY7C148  
CY7C149  
1Kx4 Static RAM  
sion is provided by an active LOW chip select (CS) input and  
three-state outputs. The CY7C148 remains in a low-power  
mode as long as the device remains unselected; i.e., (CS) is  
HIGH, thus reducing the average power requirements of the  
device. The chip select (CS) of the CY7C149 does not affect  
the power dissipation of the device.  
Features  
• Automatic power-down when deselected (7C148)  
• CMOS for optimum speed/power  
• 25-ns access time  
• Low active power  
Writing to the device is accomplished when the chip select  
(CS) and write enable (WE) inputs are both LOW. Data on the  
I/O pins (I/O0 through I/O3) is written into the memory loca-  
tions specified on the address pins (A0 through A9).  
— 440 mW (commercial)  
— 605 mW (military)  
• Low standby power (7C148)  
— 82.5 mW (25-ns version)  
— 55 mW (all others)  
Reading the device is accomplished by taking chip select (CS)  
LOW while write enable (WE) remains HIGH. Under these  
conditions, the contents of the location specified on the  
address pins will appear on the four data I/O pins.  
• 5-volt power supply ± 10% tolerance, both commercial  
and military  
• TTL-compatible inputs and outputs  
The I/O pins remain in a high-impedance state when chip se-  
lect (CS) is HIGH or write enable (WE) is LOW.  
Functional Description  
The CY7C148 and CY7C149 are high-performance CMOS  
static RAMs organized as 1024 by 4 bits. Easy memory expan-  
Logic Block Diagram  
PinConfigurations  
DIP  
Top View  
A
V
6
1
2
3
4
5
6
7
8
9
CC  
18  
17  
16  
15  
A
5
A
4
A
3
A
A
A
7
A
8
A
9
I/O  
I/O  
I/O  
I/O  
INPUTBUFFER  
0
1
14  
13  
12  
11  
10  
0
1
2
3
A
2
A
A
8
9
I/O  
0
CS  
WE  
GND  
A
I/O  
1
64x 64  
ARRAY  
7
A
C148–2  
6
I/O  
2
LCC  
A
5
Top View  
A
4
I/O  
3
CS  
2 1 1817  
POWER  
DOWN  
(7C148)  
A
A
3
4
5
6
7
16  
4
8
COLUMN  
A
A
15  
13  
9
DECODER  
A
14 I/O  
10  
WE  
0
1
2
A
13  
12  
I/O  
I/O  
11  
A
12  
A
3
8 91011  
A A  
A
0
2
1
C148–1  
C148–3  
Selection Guide  
7C148−25  
7C148−35  
7C148−45  
7C149−25  
7C149−35  
7C149−45  
Maximum Access Time (ns)  
25  
90  
35  
80  
45  
80  
25  
90  
35  
80  
45  
80  
Maximum Operating  
Current (mA)  
Commercial  
Military  
110  
10  
110  
10  
110  
110  
Maximum Standby  
Current (mA)  
Commercial  
Military  
15  
10  
10  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05059 Rev. **  
Revised September 18, 2001  
[+] Feedback  
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