Datasheet > CY7C1475V25-133BX

CY7C1475V25-133BX

更新时间： 2024-09-18 20:37:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	1015K
描述
ZBT SRAM, 1MX72, 6.5ns, CMOS, PBGA209

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1475V25-133BX 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.8	最长访问时间：	6.5 ns
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B209	内存密度：	75497472 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	72
端子数量：	209	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
组织：	1MX72	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA209,11X19,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
最小待机电流：	2.38 V	子类别：	SRAMs
表面贴装：	YES	技术：	CMOS
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

CY7C1475V25-133BX 数据手册

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第2页

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第3页

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第4页

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第5页

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第6页

浏览型号CY7C1475V25-133BX的Datasheet PDF文件第7页

CY7C1471V25

CY7C1473V25

CY7C1475V25

ADVANCE

INFORMATION

2M x 36/4M x 18/1M x 72 Flow-through

SRAM with NoBL™ Architecture

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and read-write

control (WE). BWS_cand BWS_dapply to CY7C1471V25 and

CY7C1475V25 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1475V25 only.

Features

• Zero Bus Latency™, no dead cycles between write and

read

• Supports 133-MHz bus operations

• 2M × 36/4M × 18/1M × 72 common I/O

• Fast clock-to-output times

— 5.5 ns (for 150-MHz device)

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

— 8.5 ns (for 100-MHz device)

Clock Enable (CEN) pin allows operation of the

CY7C1471V25, CY7C1473V25, and CY7C1475V25 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is HIGH, and the internal device registers

hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in

high-impedance state two cycles after chip is deselected or a

write cycle is initiated.

• Single 2.5V –5% and +5% power supply V_DD

• Separate V_DDQfor 2.5V or 1.8V I/O

• Clock Enable (CEN) pin to suspend operation

• Burst Capability—linear or interleaved burst order

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1471V25 and CY7C1473V25). 209

FBGA package for CY7C1475V25.

The CY7C1471V25,CY7C1473V25 and CY7C1475V25 have

an on-chip two-bit burst counter. In the burst mode,

CY7C1471V25, CY7C1473V25, and CY7C1475V25 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH).

Functional Description

The CY7C1471V25, CY7C1473V25, and CY7C1475V25

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100 percent bus utilization and achieves Zero

Bus Latency. They integrate 2,097,152 × 36/4,194,304 ×

18/1,048,576 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and Write

LOGIC

2M × 36/

4M × 18/

1M × 72

MEMORY

ARRAY

BWS

X = a, b,

c, d

X = a, b, X= a, b,

X = 20:0

X = 21:0

2M × 36

c, d

Mode

X = a, b

X = a, b X = a, b

4M × 18

1M × 72

X = a, b,

X = 19:0

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05287 Rev. **

Revised August 2, 2002

12 3 4 5 6 7...26

中文翻译

下载PDF

与CY7C1475V25-133BX相关器件

型号	品牌	获取价格	描述	数据表
CY7C1475V25-150BX	CYPRESS	获取价格	ZBT SRAM, 1MX72, 5.5ns, CMOS, PBGA209
CY7C1475V33	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V33-100BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V33-100BGI	CYPRESS	获取价格	ZBT SRAM, 1MX72, 8.5ns, CMOS, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
CY7C1475V33-100BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V33-117BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475V33-117BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475V33-117BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475V33-117BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1475V33-133BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

与CY7C1475V25-133BX相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

20
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

18
SL74HC10N：高性能三输入与非门解析
2024-09-03

95
AIC1781A 电池充电控制器深度解析
2024-09-03

86

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1475V25-133BX

CY7C1475V25-133BX 技术参数

CY7C1475V25-133BX 数据手册

与CY7C1475V25-133BX相关器件

与CY7C1475V25-133BX相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1475V25-133BX

CY7C1475V25-133BX 技术参数

CY7C1475V25-133BX 数据手册

与CY7C1475V25-133BX相关器件

与CY7C1475V25-133BX相关文章

您还可以找

您在本页遇到什么问题？