Datasheet > 存储 > SRAM> CY7C1473V33-133BZXI

CY7C1473V33-133BZXI

更新时间： 2024-11-07 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	1141K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

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CY7C1471V33

CY7C1473V33

CY7C1475V33

72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-ThroughSRAMwithNoBL™Architecture

Functional Description ^[1]

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst

SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471V33, CY7C1473V33 and

CY7C1475V33 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

• Supportsupto133MHzbusoperationswithzerowaitstates

• Data is transferred on every clock

• PincompatibleandfunctionallyequivalenttoZBT™devices

• Internally self timed output buffer control to eliminate the

need to use OE

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO supply (V_DDQ

)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock

cycle.Maximum access delay from the clock rise is 6.5 ns

(133-MHz device).

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self timed writes

Write operations are controlled by two or four Byte Write Select

(BW_X) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

• Asynchronous Output Enable (OE)

• CY7C1471V33, CY7C1473V33 available in

JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475V33

available in Pb-free and non-Pb-free 209-Ball FBGA

package

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

• Three Chip Enables (CE₁, CE₂, CE₃) for simple depth

expansion

• Automatic power down feature available using ZZ mode or

CE deselect

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst Capability — linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

117 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

305

275

120

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 38-05288 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 04, 2007

12 3 4 5 6 7...32

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与CY7C1473V33-133BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C147-45DMB	CYPRESS	获取价格	4K x 1 STATIC RAM
CY7C147-45KMB	CYPRESS	获取价格	Standard SRAM, 4KX1, 45ns, CMOS, CDFP18, CERPACK-18
CY7C147-45LC	CYPRESS	获取价格	Standard SRAM, 4KX1, 45ns, CMOS, CQCC18, CERAMIC, LCC-18
CY7C147-45LMB	CYPRESS	获取价格	Standard SRAM, 4KX1, 45ns, CMOS, CQCC18, CERAMIC, LCC-18
CY7C147-45PC	CYPRESS	获取价格	4K x 1 STATIC RAM
CY7C1474BV25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1474BV25-167BGXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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