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CY7C1472BV33-200BZXC PDF预览

CY7C1472BV33-200BZXC

更新时间： 2024-11-07 05:19:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 902K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1472BV33-200BZXC 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.49最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.5 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：15 mm
Base Number Matches：1

CY7C1472BV33-200BZXC 数据手册

 浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第2页浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第3页浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第4页浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第5页浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第6页浏览型号CY7C1472BV33-200BZXC的Datasheet PDF文件第7页 
CY7C1470BV33  
CY7C1472BV33, CY7C1474BV33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33  
are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back read  
or write operations with no wait states. The CY7C1470BV33,  
CY7C1472BV33, and CY7C1474BV33 are equipped with the  
advanced (NoBL) logic required to enable consecutive read or  
write operations with data being transferred on every clock cycle.  
This feature dramatically improves the throughput of data in  
systems that require frequent read or write transitions. The  
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin  
compatible and functionally equivalent to ZBT devices.  
■ Pin-compatible and functionally equivalent to ZBT™  
■ Supports 250 MHz bus operations with zero wait states  
❐ Available speed grades are 250, 200, and 167 MHz  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte Write capability  
■ Single 3.3V power supply  
■ 3.3V/2.5V IO power supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the Clock Enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Fast clock-to-output time  
❐ 3.0 ns (for 250-MHz device)  
■ Clock Enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
■ CY7C1470BV33, CY7C1472BV33 available in  
(BWa–BWd  
for  
CY7C1470BV33,  
BWa–BWb  
for  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1474BV33  
available in Pb-free and non-Pb-free 209-ball FBGA package  
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst capability—linear or interleaved burst order  
■ “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
Selection Guide  
Description  
Maximum Access Time  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
3.0  
500  
120  
Maximum Operating Current  
500  
450  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15031 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 29, 2008  
[+] Feedback  
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与CY7C1472BV33-200BZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1472BV33-200BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250AXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V25 CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-167AC CYPRESS

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 		ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1472V25-167AXC CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR

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