Datasheet > CY7C1471BV33-133AXC

CY7C1471BV33-133AXC

更新时间： 2024-11-17 15:18:43

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
32页	882K
描述
Synchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1471BV33-133AXC 数据手册

浏览型号CY7C1471BV33-133AXC的Datasheet PDF文件第2页

浏览型号CY7C1471BV33-133AXC的Datasheet PDF文件第3页

浏览型号CY7C1471BV33-133AXC的Datasheet PDF文件第4页

浏览型号CY7C1471BV33-133AXC的Datasheet PDF文件第5页

浏览型号CY7C1471BV33-133AXC的Datasheet PDF文件第6页

CY7C1471BV33

CY7C1473BV33

72-Mbit (2M × 36/4M × 18)

Flow-Through SRAM

with NoBL™ Architecture

72-Mbit (2M

× 36/4M × 18) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ No bus latency™ (NoBL™) architecture eliminates dead cycles

between write and read cycles

The CY7C1471BV33 and CY7C1473BV33 are 3.3 V,

2M × 36/4M × 18 synchronous flow through burst SRAMs

designed specifically to support unlimited true back-to-back read

or write operations without the insertion of wait states. The

CY7C1471BV33 and CY7C1473BV33 are equipped with the

advanced No Bus Latency (NoBL) logic. NoBL™ is required to

enable consecutive read or write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent write-read transitions.

■ Supports up to 133 MHz bus operations with zero wait states

■ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

■ 3.3 V/2.5 V I/O supply (V_DDQ

)

■ Fast clock-to-output times

Write operations are controlled by two or four Byte Write Select

(BW_X) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

❐ 6.5 ns (for 133 MHz device)

■ Clock enable (CEN) pin to enable clock and suspend operation

■ Synchronous self-timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ Asynchronous output enable (OE)

■ CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin

thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball

fine-pitch ball grid array (FBGA) package. CY7C1473BV33

available in JEDEC-standard Pb-free 100-pin thin quad flat

pack (TQFP)

For a complete list of related documentation, click here.

■ Three chip enables (CE₁, CE₂, CE₃) for simple depth

expansion

■ Automatic power-down feature available using ZZ mode or CE

deselect

■ IEEE 1149.1 JTAG boundary scan compatible

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum access time

133 MHz Unit

6.5

305

120

Maximum operating current

Maximum CMOS standby current

Cypress Semiconductor Corporation

Document Number: 001-15029 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 12, 2018

12 3 4 5 6 7...32

中文翻译

下载PDF

与CY7C1471BV33-133AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1471BV33-133AXCT	INFINEON	获取价格	Synchronous SRAM
CY7C1471BV33-133AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471BV33-133BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471BV33-133BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471BV33-133BZI	INFINEON	获取价格	Synchronous SRAM
CY7C1471BV33-133BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471BV33-133BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25_07	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25_13	CYPRESS	获取价格	72-Mbit (2 M x 36) Flow-Through SRAM with NoB

与CY7C1471BV33-133AXC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

14
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

8
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471BV33-133AXC

CY7C1471BV33-133AXC 数据手册

与CY7C1471BV33-133AXC相关器件

与CY7C1471BV33-133AXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471BV33-133AXC

CY7C1471BV33-133AXC 数据手册

与CY7C1471BV33-133AXC相关器件

与CY7C1471BV33-133AXC相关文章

您还可以找

您在本页遇到什么问题？