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CY7C1471BV33-117AXC PDF预览

CY7C1471BV33-117AXC

更新时间： 2024-11-16 06:51:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
32页 884K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

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CY7C1471BV33-117AXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.74
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最小待机电流：3.14 V
子类别：SRAMs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1471BV33-117AXC 数据手册

 浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第2页浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第3页浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第4页浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第5页浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第6页浏览型号CY7C1471BV33-117AXC的Datasheet PDF文件第7页 
CY7C1471BV33  
CY7C1473BV33, CY7C1475BV33  
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through  
SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33  
are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through  
burst SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471BV33, CY7C1473BV33, and  
CY7C1475BV33 are equipped with the advanced No Bus  
Latency (NoBL) logic. NoBL™ is required to enable consecutive  
read or write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput of  
data through the SRAM, especially in systems that require  
frequent write-read transitions.  
■ Supports up to 133 MHz bus operations with zero wait states  
■ Data is transferred on every clock  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow through operation  
■ Byte Write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
Clock Enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133 MHz device).  
■ 3.3V/2.5V IO supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 6.5 ns (for 133 MHz device)  
Write operations are controlled by two or four Byte Write Select  
(BWX) and a Write Enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
■ Clock Enable (CEN) pin to enable clock and suspend operation  
■ Synchronous self-timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence. For best practice recommendations,  
refer to the Cypress application note AN1064 “SRAM System  
Guidelines”.  
■ Asynchronous Output Enable (OE)  
■ CY7C1471BV33, CY7C1473BV33 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-Ball FBGA package. CY7C1475BV33  
available in Pb-free and non-Pb-free 209-Ball FBGA package  
■ Three Chip Enables (CE1, CE2, CE3) for simple depth  
expansion  
■ Automatic power down feature available using ZZ mode or CE  
deselect  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst Capability—linear or interleaved burst order  
■ Low standby power  
Selection Guide  
Description  
Maximum Access Time  
133 MHz  
6.5  
117 MHz  
8.5  
Unit  
ns  
Maximum Operating Current  
Maximum CMOS Standby Current  
305  
275  
mA  
mA  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15029 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 05, 2008  
[+] Feedback  
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CY7C1471BV33-117AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1471BV33-133AXC CYPRESS

完全替代

 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

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