5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1471BV25-100BZXC
CY7C1471BV25-100BZXC PDF预览

CY7C1471BV25-100BZXC

更新时间： 2024-11-16 05:19:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
30页 848K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

阅读下载

中文翻译

获取价格

CY7C1471BV25-100BZXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.79Is Samacsys：N
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
电源：1.8/2.5,2.5 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.275 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：15 mmBase Number Matches：1

CY7C1471BV25-100BZXC 数据手册

 浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第2页浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第3页浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第4页浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第5页浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第6页浏览型号CY7C1471BV25-100BZXC的Datasheet PDF文件第7页 
CY7C1471BV25  
CY7C1473BV25, CY7C1475BV25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25  
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through  
burst SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471BV25, CY7C1473BV25, and  
CY7C1475BV25 are equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive read or  
write operations with data transferred on every clock cycle. This  
feature dramatically improves the throughput of data through the  
SRAM, especially in systems that require frequent write-read  
transitions.  
■ Supports up to 133 MHz bus operations with zero wait states  
■ Data transfers on every clock  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow through operation  
■ Byte Write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
Clock Enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133-MHz device).  
■ 2.5V IO supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 6.5 ns (for 133-MHz device)  
Write operations are controlled by two or four Byte Write Select  
(BWX) and a Write Enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
■ Clock Enable (CEN) pin to enable clock and suspend operation  
■ Synchronous self timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide easy bank selection  
and output tri-state control. To avoid bus contention, the output  
drivers are synchronously tri-stated during the data portion of a  
write sequence.  
■ Asynchronous Output Enable (OE)  
■ CY7C1471BV25, CY7C1473BV25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1475BV25  
available in Pb-free and non-Pb-free 209-ball FBGA package.  
For best practice recommendations, refer to the Cypress appli-  
cation note AN1064, SRAM System Guidelines.  
■ Three Chip Enables (CE1, CE2, CE3) for simple depth  
expansion.  
■ Automatic power down feature available using ZZ mode or CE  
deselect.  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst Capability - linear or interleaved burst order  
■ Low standby power  
Selection Guide  
Description  
Maximum Access Time  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Operating Current  
305  
275  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15013 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 29, 2008  
[+] Feedback  
1234567...30

中文翻译

下载PDF

与CY7C1471BV25-100BZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1471BV25-100BZXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133AXC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133AXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133AXI INFINEON

获取价格

 		Synchronous SRAM
CY7C1471BV25-133BZC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133BZI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133BZXC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV25-133BZXI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471BV33 CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471BV33_11 CYPRESS

获取价格

 		72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture

与CY7C1471BV25-100BZXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证