Datasheet > CY7C1461AV33_06

CY7C1461AV33_06

更新时间： 2024-09-28 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	506K
描述
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL⑩ Architecture

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CY7C1461AV33_06 数据手册

CY7C1461AV33

CY7C1463AV33

CY7C1465AV33

36-Mbit (1M x 36/2 M x 18/512K x 72)

Flow-Through SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33

is equipped with the advanced No Bus Latency (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data through the

SRAM, especially in systems that require frequent Write-Read

transitions.

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin-compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• CY7C1461AV33, CY7C1463AV33 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1465AV33 available in lead-free and non-lead-free

209-ball FBGA package

• Three chip enables for simple depth expansion

• Automatic Power-down feature available using ZZ

mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

310

290

Maximum CMOS Standby Current

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05356 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 23, 2006

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与CY7C1461AV33_06相关器件

型号	品牌	获取价格	描述	数据表
CY7C1461AV33_08	CYPRESS	获取价格	36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33_11	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM with NoBL Architecture
CY7C1461AV33_12	CYPRESS	获取价格	36-Mbit (1 M Ã 36/2 M Ã 18) Flow-Through SR
CY7C1461AV33-100AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-133AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr

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