Datasheet > CY7C1447V33-117BX

CY7C1447V33-117BX

更新时间： 2024-09-21 06:17:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	605K
描述
Standard SRAM, 512KX72, 7.5ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209

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CY7C1441V33

CY7C1443V33

CY7C1447V33

PRELIMINARY

1M x 36/2M x 18/512K x 72

Flow-through SRAM

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and

ADV), Write Enables (BW_a, BW_b, BW_c, BW_d, BW_e, BW_f, BW_g,

BW_h, and BWe), and Global Write (GW).

Features

• Supports 133-MHz bus operations

• 1M x 36/2M x 18/512K x 72 common I/O

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (DQ), enabled

by OE, are also asynchronous.

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Byte Write Enable and Global Write control

• Burst Capability – linear or interleaved burst order

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or address status controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BW_a

controls DQ1–DQ8 and DP1. BW_bcontrols DQ9–DQ16 and

DP2. BW_ccontrols DQ17–DQ24 and DP3. BW_dcontrols

DQ25–DQ32 and DP4. BW_econtrols DQ33–DQ40 and DP5.

BW_fcontrols DQ41–DQ48 and DP6. BW_gcontrols

DQ49–DQ56 and DP7. BW_hcontrols DQ57–DQ64 and DP8.

BW_a, BW_b, BW_c, BW_d, BW_e, BW_f, BW_g, and BW_hcan be

active only with BWE being LOW. GW being LOW causes all

bytes to be written. Write pass-through capability allows

written data available at the output for the immediately next

Read cycle. This device also incorporates pipelined enable

circuit for easy depth expansion without penalizing system

performance.

• Automatic power down available using ZZ mode or CE

deselect

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA, 165-ball FBGA, and

100-pin TQFP packages (CY7C1441V33 and

CY7C1443V33). 209 FBGA package for CY7C1447V33.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1441V33/CY7C1443V33/CY7C1447V33 SRAMs

integrate 1,048,576 x 36/2,097,152 x18 and 524,288 x 72

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

All inputs and outputs of theCY7C1441V33/CY7C1443V33/

CY7C1447V33 are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram CY7C1441V33 – 1M × 36

MODE

(A_[1;0]

)

CLK

ADV

ADSC

BURST

COUNTER

CLR

ADSP

ADDRESS

1M X36

A_[19:0]

MEMORY

ARRAY

DQ_d, DP_d

BYTEWRITE

REGISTERS

BWE

DQ_c, DP_c

BYTEWRITE

REGISTERS

DQ_b, DP_b

BYTEWRITE

REGISTERS

DQ_a, DP_a

BYTEWRITE

REGISTERS

ENABLE CE

OUTPUT

REGISTERS

INPUT

REGISTERS

CLK

ENABLE DELAY

CLK

SLEEP

CONTROL

DQ_a,b,c,d

DP_a,b,c,d

Cypress Semiconductor Corporation

Document #: 38-05185 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 13, 2002

12 3 4 5 6 7...28

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与CY7C1447V33-117BX相关器件

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CY7C144AV	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV_12	CYPRESS	获取价格	3.3 V 8 K / 16 K Ã 8 Asynchronous Dual-Port
CY7C144AV-20AC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-20JC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25AC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25AXC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25JC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25JXC	CYPRESS	获取价格	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
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