Datasheet > 存储 > SRAM> CY7C1447AV33-100BGXI

CY7C1447AV33-100BGXI

更新时间： 2024-01-17 09:33:05

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	567K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

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CY7C1447AV33-100BGXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA, BGA209,11X19,40
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.84	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH ARCHITECTURE	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B209
JESD-609代码：	e1	长度：	22 mm
内存密度：	37748736 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	72	湿度敏感等级：	3
功能数量：	1	端子数量：	209
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA209,11X19,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.96 mm	最大待机电流：	0.12 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.29 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	14 mm	Base Number Matches：	1

CY7C1447AV33-100BGXI 数据手册

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CY7C1441AV33

CY7C1443AV33

CY7C1447AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 1M x 36/2M x 18/512K x 72 common I/O

• 3.3V core power supply

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 are

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through

SRAMs, respectively designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133-MHz version). A 2-bit

on-chip counter captures the first address in a burst and incre-

ments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

• 2.5V or 3.3V I/O power supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

and ADV), Write Enables (BW_x, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the Processor Address Strobe

(ADSP) or the cache Controller Address Strobe (ADSC)

inputs. Address advancement is controlled by the Address

Advancement (ADV) input.

• CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1447AV33 available in lead-free and non-lead-free

209-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The

CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

310

290

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05357 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 23, 2006

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与CY7C1447AV33-100BGXI相关器件

型号	品牌	描述	获取价格	数据表
CY7C1447AV33-133BGC	CYPRESS	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM	获取价格
CY7C1447AV33-133BGI	CYPRESS	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM	获取价格
CY7C1447AV33-133BGXC	CYPRESS	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM	获取价格
CY7C1447AV33-133BGXI	CYPRESS	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM	获取价格
CY7C1447V33-117BX	CYPRESS	Standard SRAM, 512KX72, 7.5ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209	获取价格
CY7C144AV	CYPRESS	3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM	获取价格

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