Datasheet > CY7C1447AV25

CY7C1447AV25

更新时间： 2024-12-01 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	517K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1447AV25 数据手册

CY7C1441AV25

CY7C1443AV25

CY7C1447AV25

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 1M x 36/2M x 18/512K x 72 common I/O

• 2.5V core power supply

The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 are 2.5V,

1M x 36/2M x 18/512K x 72 Synchronous Flow-through

SRAMs, respectively designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133-MHz version). A 2-bit

on-chip counter captures the first address in a burst and incre-

ments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth- expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

and ADV), Write Enables (BW_x, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 allows

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the Processor Address Strobe

(ADSP) or the cache Controller Address Strobe (ADSC)

inputs. Address advancement is controlled by the Address

Advancement (ADV) input.

• CY7C1441AV25, CY7C1443AV25 available in lead-free

100-pin TQFP package, lead-free and non-lead-free

165-ball FBGA package. CY7C1447AV25 available in

lead-free and non-lead-free 209-ball FBGA package

• JTAG boundary scan for FBGA package

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25

operates from a +2.5V core power supply while all outputs may

operate with either a +2.5V or 1.8V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

270

250

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05349 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 21, 2006

12 3 4 5 6 7...31

中文翻译

下载PDF

与CY7C1447AV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1447AV25-100BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-100BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-100BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-100BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-133BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-133BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-133BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV25-133BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV33	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
CY7C1447AV33-100BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

与CY7C1447AV25相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1447AV25

CY7C1447AV25 数据手册

与CY7C1447AV25相关器件

与CY7C1447AV25相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1447AV25

CY7C1447AV25 数据手册

与CY7C1447AV25相关器件

与CY7C1447AV25相关文章

您还可以找

您在本页遇到什么问题？