CY7C1440V33
CY7C1442V33
CY7C1446V33
PRELIMINARY
1M x 36/2M x 18/512K x 72
Pipelined SRAM
Chip Enable (CE), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWa, BWb, BWc, BWd, and BWE), and
Global Write (GW).
Features
• Fast clock speed: 250, 200, and 167 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast access time: 2.7, 3.0 and 3.5 ns
• Optimal for depth expansion
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQa,b,c,d) and the data
parity (DPa,b,c,d
)
outputs, enabled by OE, are also
asynchronous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1440V33, DQa,b and
DPa,b apply to CY7C1442V33, and DQa,b,c,d,e,f,g,h and
DPa,b,c,d,e,f,g,h apply to CY7C1446V33. a,b,c,d,e,f,g,h each
are eight bits wide in the case of DQ and one bit wide in the
case of DP.
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to eight bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
• Available in 119-ball bump BG,165-ball FBGA package,
and 100-pin TQFP packages (CY7C1440V33 and
CY7C1442V33). 209 FBGA package for CY7C1446V33.
controls DQa and DPa. BWb controls DQ and DP . BWc
b
b
controls DQc and DPd. BWd controls DQ and DPd. BWe
controls DQe and DPe. BWf controls DQf and DPf. BWg
controls DQg and DPg. BWh controls DQh and DPh. BWa,
BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be active
only with BWE LOW. GW LOW causes all bytes to be written.
Write pass-through capability allows written data available at
the output for the immediately next Read cycle. This device
also incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1440V33, CY7C1442V33, and CY7C1446V33
SRAMs integrate 1,048,576 x 36/2,097,152 x 18 and 524,288
x 72 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
All inputs and outputs of the CY7C1440V33, CY7C1442V33,
and the CY7C1446V33 are JEDEC-standard JESD8-5
-compatible.
Selection Guide[1]
CY7C1440V33
CY7C1446V33
CY7C1446V33
-300
CY7C1440V33
CY7C1446V33
CY7C1446V33
-250
CY7C1440V33
CY7C1446V33
CY7C1446V33
-200
CY7C1440V33
CY7C1446V33
CY7C1446V33
-167
Unit
ns
Maximum Access Time
2.3
2.7
3.0
3.5
Maximum Operating Current
Com’l
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Maximum CMOS Standby Current
Note:
1. Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05184 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 13, 2002
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