Datasheet > CY7C1446AV33

CY7C1446AV33

更新时间： 2024-11-30 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	392K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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CY7C1446AV33 数据手册

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

PRELIMINARY

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM

integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72

SRAM cells with advanced synchronous peripheral circuitry

• Available speed grades are 250, 200,167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE₁), depth-expansion Chip Enables (CE₂and

CE₃^[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (BW_Xand BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the

ZZ pin.

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 3.2 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard 100-pin TQFP, 165-Ball

fBGA and 209-Ball fBGA packages

causes all bytes to be written.

LOW

The

CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

2.6

200 MHz

3.2

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

475

425

375

100

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 fBGA package only.

Cypress Semiconductor Corporation

Document #: 38-05383 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 31, 2005

12 3 4 5 6 7...27

中文翻译

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与CY7C1446AV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1446AV33-167BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-167BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-167BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-167BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-200BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-200BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-200BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-200BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-250BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
CY7C1446AV33-250BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

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