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CY7C1441AV33_11 PDF预览

CY7C1441AV33_11

更新时间: 2024-10-26 09:44:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
34页 1120K
描述
36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM

CY7C1441AV33_11 数据手册

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CY7C1441AV33  
CY7C1443AV33, CY7C1447AV33  
36-Mbit (1 M × 36/2 M × 18/512 K × 72)  
Flow-Through SRAM  
36-Mbit (1  
M × 36/2 M × 18/512 K × 72) Flow-Through SRAM  
Features  
Functional Description  
Supports 133-MHz bus operations  
1 M × 36/2 M × 18/512 K × 72 common IO  
3.3 V core power supply  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are  
3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through  
SRAMs, respectively designed to interface with high-speed  
microprocessors with minimum glue logic. Maximum access  
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip  
counter captures the first address in a burst and increments the  
address automatically for the rest of the burst access. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
2.5 V or 3.3 V IO power supply  
Fast clock-to-output times  
6.5 ns (133-MHz version)  
Provide high-performance 2-1-1-1 access rate  
User-selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWx, and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the ZZ  
pin.  
Separate processor and controller address strobes  
Synchronous self-timed write  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows  
either interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst sequence,  
while a LOW selects a linear burst sequence. Burst accesses  
can be initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement (ADV)  
input.  
Asynchronous output enable  
CY7C1441AV33,  
CY7C1443AV33  
available  
in  
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and  
non Pb-free 165-ball FBGA package. CY7C1447AV33  
available in Pb-free and non Pb-free 209-ball FBGA package  
IEEE 1149.1 JTAG-Compatible Boundary Scan  
“ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or Address  
Strobe Controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
The  
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33  
operates from a +3.3 V core power supply while all outputs may  
operate with either a +2.5 or +3.3 V supply. All inputs and outputs  
are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
Description  
Maximum Access Time  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Operating Current  
310  
290  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Note  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05357 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 23, 2011  
[+] Feedback  

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