Datasheet > CY7C1441AV33_11

CY7C1441AV33_11

更新时间： 2024-10-26 09:44:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
34页	1120K
描述
36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1441AV33_11 数据手册

CY7C1441AV33

CY7C1443AV33, CY7C1447AV33

36-Mbit (1 M × 36/2 M × 18/512 K × 72)

Flow-Through SRAM

36-Mbit (1

M × 36/2 M × 18/512 K × 72) Flow-Through SRAM

Features

Functional Description

■ Supports 133-MHz bus operations

■ 1 M × 36/2 M × 18/512 K × 72 common IO

■ 3.3 V core power supply

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33^[1]are

3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through

SRAMs, respectively designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip

counter captures the first address in a burst and increments the

address automatically for the rest of the burst access. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE₁), depth-expansion Chip Enables (CE₂and

■ 2.5 V or 3.3 V IO power supply

■ Fast clock-to-output times

❐ 6.5 ns (133-MHz version)

■ Provide high-performance 2-1-1-1 access rate

■ User-selectable burst counter supporting Intel^Pentium^

interleaved or linear burst sequences

CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (BW_x, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

■ Separate processor and controller address strobes

■ Synchronous self-timed write

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst sequence,

while a LOW selects a linear burst sequence. Burst accesses

can be initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement (ADV)

input.

■ Asynchronous output enable

■ CY7C1441AV33,

CY7C1443AV33

available

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and

non Pb-free 165-ball FBGA package. CY7C1447AV33

available in Pb-free and non Pb-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

The

CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

operates from a +3.3 V core power supply while all outputs may

operate with either a +2.5 or +3.3 V supply. All inputs and outputs

are JEDEC-standard JESD8-5-compatible.

Selection Guide

Description

Maximum Access Time

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Operating Current

310

290

Maximum CMOS Standby Current

120

Note

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document Number: 38-05357 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 23, 2011

[+] Feedback

12 3 4 5 6 7...34

中文翻译

下载PDF

与CY7C1441AV33_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1441AV33_13	CYPRESS	获取价格	36-Mbit (1 M x 36) Flow-Through SRAM
CY7C1441AV33-100AXC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-100AXI	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-100BZC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1441AV33-100BZXC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1441AV33-100BZXI	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1441AV33-133AXC	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-133AXI	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133AXIT	CYPRESS	获取价格	Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100

与CY7C1441AV33_11相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

5
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

4
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

35
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

43

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1441AV33_11

CY7C1441AV33_11 数据手册

与CY7C1441AV33_11相关器件

与CY7C1441AV33_11相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1441AV33_11

CY7C1441AV33_11 数据手册

与CY7C1441AV33_11相关器件

与CY7C1441AV33_11相关文章

您还可以找

您在本页遇到什么问题？