Datasheet > CY7C1441AV33

CY7C1441AV33

更新时间： 2024-10-26 05:19:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	567K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

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CY7C1441AV33 数据手册

CY7C1441AV33

CY7C1443AV33

CY7C1447AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 1M x 36/2M x 18/512K x 72 common I/O

• 3.3V core power supply

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 are

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through

SRAMs, respectively designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133-MHz version). A 2-bit

on-chip counter captures the first address in a burst and incre-

ments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃), Burst Control inputs (ADSC, ADSP,

• 2.5V or 3.3V I/O power supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

and ADV), Write Enables (BW_x, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows

either interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the Processor Address Strobe

(ADSP) or the cache Controller Address Strobe (ADSC)

inputs. Address advancement is controlled by the Address

Advancement (ADV) input.

• CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1447AV33 available in lead-free and non-lead-free

209-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The

CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

310

290

120

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05357 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 23, 2006

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与CY7C1441AV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1441AV33_11	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33_13	CYPRESS	获取价格	36-Mbit (1 M x 36) Flow-Through SRAM
CY7C1441AV33-100AXC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-100AXI	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-100BZC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1441AV33-100BZXC	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1441AV33-100BZXI	CYPRESS	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1441AV33-133AXC	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133AXCT	CYPRESS	获取价格	Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-133AXI	CYPRESS	获取价格	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM

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