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CY7C1441AV33-133AXC PDF预览

CY7C1441AV33-133AXC

更新时间： 2024-10-26 09:44:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
34页 1120K
描述
36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM

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CY7C1441AV33-133AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：8.58
最长访问时间：6.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：37748736 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.31 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mm

CY7C1441AV33-133AXC 数据手册

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CY7C1441AV33  
CY7C1443AV33, CY7C1447AV33  
36-Mbit (1 M × 36/2 M × 18/512 K × 72)  
Flow-Through SRAM  
36-Mbit (1  
M × 36/2 M × 18/512 K × 72) Flow-Through SRAM  
Features  
Functional Description  
■ Supports 133-MHz bus operations  
■ 1 M × 36/2 M × 18/512 K × 72 common IO  
■ 3.3 V core power supply  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are  
3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through  
SRAMs, respectively designed to interface with high-speed  
microprocessors with minimum glue logic. Maximum access  
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip  
counter captures the first address in a burst and increments the  
address automatically for the rest of the burst access. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered Clock Input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and  
■ 2.5 V or 3.3 V IO power supply  
■ Fast clock-to-output times  
❐ 6.5 ns (133-MHz version)  
■ Provide high-performance 2-1-1-1 access rate  
■ User-selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write  
Enables (BWx, and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the ZZ  
pin.  
■ Separate processor and controller address strobes  
■ Synchronous self-timed write  
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows  
either interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst sequence,  
while a LOW selects a linear burst sequence. Burst accesses  
can be initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement (ADV)  
input.  
■ Asynchronous output enable  
■ CY7C1441AV33,  
CY7C1443AV33  
available  
in  
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and  
non Pb-free 165-ball FBGA package. CY7C1447AV33  
available in Pb-free and non Pb-free 209-ball FBGA package  
■ IEEE 1149.1 JTAG-Compatible Boundary Scan  
■ “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or Address  
Strobe Controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
The  
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33  
operates from a +3.3 V core power supply while all outputs may  
operate with either a +2.5 or +3.3 V supply. All inputs and outputs  
are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
Description  
Maximum Access Time  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Operating Current  
310  
290  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Note  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05357 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 23, 2011  
[+] Feedback  
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中文翻译

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CY7C1441AV33-133AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1441KV33-133AXC CYPRESS

完全替代

 Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,
CY7C1441AV33-133AXCT CYPRESS

类似代替

 Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-133AXI CYPRESS

类似代替

 36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM

与CY7C1441AV33-133AXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1441AV33-133AXCT CYPRESS

获取价格

 		Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1441AV33-133AXI CYPRESS

获取价格

 		36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133AXIT CYPRESS

获取价格

 		Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100
CY7C1441AV33-133BZC CYPRESS

获取价格

 		Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1441AV33-133BZI CYPRESS

获取价格

 		36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441AV33-133BZXC CYPRESS

获取价格

 		Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1441AV33-133BZXI CYPRESS

获取价格

 		36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM
CY7C1441KV25-133BZXI CYPRESS

获取价格

 		Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165, FBGA-165
CY7C1441KV33 CYPRESS

获取价格

 		36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
CY7C1441KV33-133AXC CYPRESS

获取价格

 		Standard SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026,

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