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CY7C1441AV25-133BZXIT PDF预览

CY7C1441AV25-133BZXIT

更新时间: 2024-10-26 21:16:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
33页 1379K
描述
Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165

CY7C1441AV25-133BZXIT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:6.5 ns最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
内存密度:37748736 bit内存集成电路类型:STANDARD SRAM
内存宽度:36端子数量:165
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL电源:1.8/2.5,2.5 V
认证状态:Not Qualified最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.27 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
Base Number Matches:1

CY7C1441AV25-133BZXIT 数据手册

 浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第2页浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第3页浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第4页浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第5页浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第6页浏览型号CY7C1441AV25-133BZXIT的Datasheet PDF文件第7页 
CY7C1441AV25  
CY7C1447AV25  
36-Mbit (1M × 36/512K × 72)  
Flow-Through SRAM  
36-Mbit (1M  
× 36/512K × 72) Flow-Through SRAM  
Features  
Functional Description  
Supports 133 MHz bus operations  
1M × 36/512K × 72 common I/O  
2.5 V core power supply  
The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1M × 36/512K × 72  
Synchronous Flow-Through SRAMs, designed to interface with  
high speed microprocessors with minimum glue logic. Maximum  
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit  
on-chip counter captures the first address in a burst and  
increments the address automatically for the rest of the burst  
access. All synchronous inputs are gated by registers controlled  
2.5 V I/O power supply  
Fast clock-to-output times  
6.5 ns (133 MHz version)  
by  
a
positive edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address pipelining Chip Enable (CE1), depth expansion Chip  
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and  
ADV), Write Enables (BWx and BWE), and Global Write (GW).  
Asynchronous inputs include the Output Enable (OE) and the ZZ  
pin.  
Provide high performance 2-1-1-1 access rate  
User selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
Separate processor and controller address strobes  
Synchronous self timed write  
The CY7C1441AV25/CY7C1447AV25 allows either interleaved  
or linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence and a LOW selects  
a linear burst sequence. Burst accesses can be initiated with the  
Processor Address Strobe (ADSP) or the cache Controller  
Address Strobe (ADSC) inputs. Address advancement is  
controlled by the Address Advancement (ADV) input.  
Asynchronous output enable  
CY7C1441AV25 available in Pb-free 165-ball FBGA package.  
CY7C1447AV25 available in non Pb-free 209-ball FBGA  
package.  
JTAG boundary scan for FBGA package  
ZZ sleep mode option  
Addresses and chip enables are registered at rising edge of  
clock when either ADSP or ADSC are active. Subsequent burst  
addresses can be internally generated as controlled by the ADV.  
operates from a  
+2.5 V core power supply while all outputs may operate with  
either +2.5 supply. All inputs and outputs are  
The CY7C1441AV25/CY7C1447AV25  
a
V
JEDEC-standard JESD8-5 compatible.  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum Access Time  
133 MHz Unit  
6.5  
270  
120  
ns  
Maximum Operating Current  
mA  
mA  
Maximum CMOS Standby Current  
Cypress Semiconductor Corporation  
Document Number: 001-75380 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 7, 2016  
 
 

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