Datasheet > 存储 > SRAM> CY7C1429JV18-300BZI

CY7C1429JV18-300BZI

更新时间： 2024-12-01 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	657K
描述
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1422JV18, CY7C1429JV18

CY7C1423JV18, CY7C1424JV18

36-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

Features

Functional Description

■

36 Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

300 MHz clock for high bandwidth

The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and

CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Double Data Rate Separate I/O (DDR-II SIO)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1422JV18, two 9-bit words in the case of CY7C1429JV18,

two 18-bit words in the case of CY7C1423JV18, and two 36-bit

words in the case of CY7C1424JV18 that burst sequentially into

or out of the device.

2-word burst for reducing address bus frequency

Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■

Synchronous internally self-timed writes

1.8V core power supply with HSTL inputs and outputs

Variable drive HSTL output buffers

Expanded HSTL output voltage (1.4V–V_DD

)

Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

CY7C1422JV18 – 4M x 8

CY7C1429JV18 – 4M x 9

CY7C1423JV18 – 2M x 18

CY7C1424JV18 – 1M x 36

Selection Guide

Description

300 MHz

300

267 MHz

267

250 MHz

250

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

825

740

700

845

750

700

x18

x36

880

790

740

980

860

800

Cypress Semiconductor Corporation

Document #: 001-44699 Rev. *B

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 31, 2009

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与CY7C1429JV18-300BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1429JV18-300BZXC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429KV18	CYPRESS	获取价格	36-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C142AV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C142BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C143	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C143-20JC	ETC	获取价格	x16 Dual-Port SRAM
CY7C143-20JCR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 20ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-20JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 20ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C143-25JC	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM

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