5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1429JV18-267BZI
CY7C1429JV18-267BZI PDF预览

CY7C1429JV18-267BZI

更新时间： 2024-12-01 06:51:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
28页 657K
描述
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

CY7C1429JV18-267BZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：267 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：17 mm
内存密度：37748736 bit内存集成电路类型：DDR SRAM
内存宽度：9湿度敏感等级：3
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX9
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.31 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.75 mA最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

CY7C1429JV18-267BZI 数据手册

 浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第2页浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第3页浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第4页浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第5页浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第6页浏览型号CY7C1429JV18-267BZI的Datasheet PDF文件第7页 
CY7C1422JV18, CY7C1429JV18  
CY7C1423JV18, CY7C1424JV18  
36-Mbit DDR-II SIO SRAM 2-Word  
Burst Architecture  
Features  
Functional Description  
■
■
■
■
36 Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)  
300 MHz clock for high bandwidth  
The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and  
CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs,  
equipped with Double Data Rate Separate I/O (DDR-II SIO)  
architecture. The DDR-II SIO consists of two separate ports: the  
read port and the write port to access the memory array. The  
read port has data outputs to support read operations and the  
write port has data inputs to support write operations. The DDR-II  
SIO has separate data inputs and data outputs to completely  
eliminate the need to “turn-around” the data bus required with  
common I/O devices. Access to each port is accomplished  
through a common address bus. Addresses for read and write  
are latched on alternate rising edges of the input (K) clock. Write  
data is registered on the rising edges of both K and K. Read data  
is driven on the rising edges of C and C if provided, or on the  
rising edge of K and K if C/C are not provided. Each address  
location is associated with two 8-bit words in the case of  
CY7C1422JV18, two 9-bit words in the case of CY7C1429JV18,  
two 18-bit words in the case of CY7C1423JV18, and two 36-bit  
words in the case of CY7C1424JV18 that burst sequentially into  
or out of the device.  
2-word burst for reducing address bus frequency  
Double Data Rate (DDR) interfaces  
(data transferred at 600 MHz) at 300 MHz  
■
■
■
Two input clocks (K and K) for precise DDR timing  
❐
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
■
■
■
■
■
■
■
■
Synchronous internally self-timed writes  
1.8V core power supply with HSTL inputs and outputs  
Variable drive HSTL output buffers  
Expanded HSTL output voltage (1.4V–VDD  
)
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1 compatible test access port  
Asynchronous inputs include an output impedance matching  
input (ZQ). Synchronous data outputs are tightly matched to the  
two output echo clocks CQ/CQ, eliminating the need to capture  
data separately from each individual DDR-II SIO SRAM in the  
system design. Output data clocks (C/C) enable maximum  
system clocking and data synchronization flexibility.  
Delay Lock Loop (DLL) for accurate data placement  
Configurations  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
CY7C1422JV18 – 4M x 8  
CY7C1429JV18 – 4M x 9  
CY7C1423JV18 – 2M x 18  
CY7C1424JV18 – 1M x 36  
Selection Guide  
Description  
300 MHz  
300  
267 MHz  
267  
250 MHz  
250  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
x8  
x9  
825  
740  
700  
845  
750  
700  
x18  
x36  
880  
790  
740  
980  
860  
800  
Cypress Semiconductor Corporation  
Document #: 001-44699 Rev. *B  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised July 31, 2009  
[+] Feedback  
1234567...28

中文翻译

下载PDF

与CY7C1429JV18-267BZI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1429JV18-267BZXC CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-267BZXI CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-300BZC CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-300BZI CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-300BZXC CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429JV18-300BZXI CYPRESS

获取价格

 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1429KV18 CYPRESS

获取价格

 		36-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C142AV18 CYPRESS

获取价格

 		RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C142BV18 CYPRESS

获取价格

 		RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C143 CYPRESS

获取价格

 		2K x 16 Dual-Port Static RAM

与CY7C1429JV18-267BZI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证