Datasheet > 存储 > SRAM> CY7C1426KV18-250BZCT

CY7C1426KV18-250BZCT

更新时间： 2024-11-27 12:57:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	921K
描述
Standard SRAM, 4MX9, 0.45ns, CMOS, PBGA165,

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CY7C1426KV18-250BZCT 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.87
最长访问时间：	0.45 ns	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
内存密度：	37748736 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	9	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX9
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	最大待机电流：	0.26 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.46 mA	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

CY7C1426KV18-250BZCT 数据手册

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CY7C1411KV18, CY7C1426KV18

CY7C1413KV18, CY7C1415KV18

36-Mbit QDR^®II SRAM 4-Word

Burst Architecture

36-Mbit QDR^®II SRAM 4-Word Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1411KV18 – 4 M × 8

CY7C1426KV18 – 4 M × 9

CY7C1413KV18 – 2 M × 18

CY7C1415KV18 – 1 M × 36

■ 333 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double data rate (DDR) Interfaces on both read and write ports

(data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and

CY7C1415KV18 are 1.8 V synchronous pipelined SRAMs,

equipped with QDR II architecture. QDR II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turnaround” the data bus that exists with common

I/O devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR II read and write ports are independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with four 8-bit words (CY7C1411KV18), 9-bit words

(CY7C1426KV18), 18-bit words (CY7C1413KV18), or 36-bit

words (CY7C1415KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in × 8, × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V (±0.1 V); I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

Maximum operating current

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

× 8

× 9

560

520

460

400

360

560

520

460

400

360

× 18

× 36

570

540

470

410

370

790

730

640

540

480

Cypress Semiconductor Corporation

Document Number: 001-57826 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 1, 2011

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与CY7C1426KV18-250BZCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1426KV18-250BZXC	CYPRESS	获取价格	36-Mbit QDR? II SRAM 4-Word Burst Architecture
CY7C1426KV18-300BZC	CYPRESS	获取价格	36-Mbit QDR? II SRAM 4-Word Burst Architecture
CY7C1426KV18-300BZCT	CYPRESS	获取价格	Standard SRAM, 4MX9, 0.45ns, CMOS, PBGA165,
CY7C1426KV18-300BZXC	CYPRESS	获取价格	36-Mbit QDR? II SRAM 4-Word Burst Architecture
CY7C1426KV18-333BZC	CYPRESS	获取价格	36-Mbit QDR? II SRAM 4-Word Burst Architecture
CY7C1427AV18	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427AV18-167BZC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427AV18-167BZI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427AV18-167BZXC	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427AV18-167BZXI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture

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