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CY7C1424AV18-250BZI PDF预览

CY7C1424AV18-250BZI

更新时间： 2024-11-24 05:19:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
28页 461K
描述
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1424AV18-250BZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.72
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTUREI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：17 mm内存密度：37748736 bit
内存集成电路类型：DDR SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.25 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.7 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
Base Number Matches：1

CY7C1424AV18-250BZI 数据手册

 浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第2页浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第3页浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第4页浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第5页浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第6页浏览型号CY7C1424AV18-250BZI的Datasheet PDF文件第7页 
CY7C1422AV18  
CY7C1429AV18  
CY7C1423AV18  
CY7C1424AV18  
36-Mbit DDR-II SIO SRAM 2-Word  
Burst Architecture  
Features  
Functional Description  
• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)  
• 300-MHz clock for high bandwidth  
The CY7C1422V18, CY7C1429AV18, CY7C1423V18,  
CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs  
equipped with DDR-II SIO (Double Data Rate Separate I/O)  
architecture. The DDR-II SIO consists of two separate ports to  
access the memory array. The Read port has dedicated Data  
outputs and the Write port has dedicated Data inputs to  
completely eliminate the need to “turn around’ the data bus  
required with common I/O devices. Access to each port is  
accomplished using a common address bus. Addresses for  
Read and Write are latched on alternate rising edges of the  
input (K) clock. Write data is registered on the rising edges of  
both K and K. Read data is driven on the rising edges of C and  
C if provided, or on the rising edge of K and K if C/C are not  
provided. Each address location is associated with two 8-bit  
words in the case of CY7C1422AV18, two 9-bit words in the  
case of CY7C1429AV18, two 18-bit words in the case of  
CY7C1423AV18, and two 36-bit words in the case of  
CY7C1424AV18, that burst sequentially into or out of the  
device.  
• 2-Word burst for reducing address bus frequency  
• Double Data Rate (DDR) interfaces  
(data transferred at 600 MHz) @ 300 MHz  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Two input clocks for output data (C and C) to minimize  
clock-skew and flight-time mismatches  
• Echo clocks (CQ and CQ) simplify data capture in  
high-speed systems  
• Synchronous internally self-timed writes  
• 1.8V core power supply with HSTL inputs and outputs  
• Variable drive HSTL output buffers  
• Expanded HSTL output voltage (1.4V–VDD  
)
Asynchronous inputs include output impedance matching  
input (ZQ). Synchronous data outputs are tightly matched to  
the two output echo clocks CQ/CQ, eliminating the need for  
separately capturing data from each individual DDR-II SIO  
SRAM in the system design. Output data clocks (C/C) enable  
maximum system clocking and data synchronization flexibility.  
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)  
• Offered in both lead-free and non lead-free packages  
• JTAG 1149.1 compatible test access port  
• Delay Lock Loop (DLL) for accurate data placement  
All synchronous inputs pass through input registers controlled  
by the K/K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clock. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Configuration  
CY7C1422AV18–4M x 8  
CY7C1429AV18–4M x 9  
CY7C1423AV18–2M x18  
CY7C1424AV18–1M x 36  
Selection Guide  
300 MHz  
300  
278 MHz  
250 MHz  
250  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
278  
775  
825  
700  
600  
500  
Cypress Semiconductor Corporation  
Document Number: 38-05617 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 26, 2006  
[+] Feedback  
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CY7C1424AV18-250BZXC CYPRESS

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CY7C1424AV18-250BZXI CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-278BZXC CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-278BZXI CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-300BZC CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-300BZI CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-300BZXC CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424AV18-300BZXI CYPRESS

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 		36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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