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CY7C1423KV18-300BZC PDF预览

CY7C1423KV18-300BZC

更新时间: 2024-11-06 14:56:11
品牌 Logo 应用领域
英飞凌 - INFINEON 双倍数据速率
页数 文件大小 规格书
31页 787K
描述
DDR-II SIO

CY7C1423KV18-300BZC 数据手册

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CY7C1423KV18/CY7C1424KV18  
36-Mbit DDR II SIO SRAM Two-Word  
Burst Architecture  
36-Mbit DDR II SIO SRAM Two-Word Burst Architecture  
Features  
Configurations  
36-Mbit density (2M × 18, 1M × 36)  
CY7C1423KV18 – 2M × 18  
CY7C1424KV18 – 1M × 36  
333 MHz clock for high bandwidth  
Two-word burst for reducing address bus frequency  
Functional Description  
Double data rate (DDR) interfaces (data transferred at  
666 MHz) at 333 MHz  
The CY7C1423KV18, and CY7C1424KV18 are 1.8  
V
synchronous pipelined SRAMs, equipped with DDR II SIO  
(double data rate separate I/O) architecture. The DDR II SIO  
consists of two separate ports: the read port and the write port to  
access the memory array. The read port has data outputs to  
support read operations and the write port has data inputs to  
support write operations. The DDR II SIO has separate data  
inputs and data outputs to completely eliminate the need to  
“turnaround” the data bus required with common I/O devices.  
Access to each port is accomplished through a common address  
bus. Addresses for read and write are latched on alternate rising  
edges of the input (K) clock. Write data is registered on the rising  
edges of both K and K. Read data is driven on the rising edges  
of C and C if provided, or on the rising edge of K and K if C/C are  
not provided. Each address location is associated with two 18-bit  
words in the case of CY7C1423KV18, and two 36-bit words in  
the case of CY7C1424KV18 that burst sequentially into or out of  
the device.  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Synchronous internally self timed writes  
DDR II operates with 1.5 cycle read latency when DOFF is  
asserted HIGH  
Operatessimilarto DDR Idevice with 1 cycle read latencywhen  
DOFF is asserted LOW  
1.8 V core power supply with HSTL inputs and outputs  
Variable drive HSTL output buffers  
Asynchronous inputs include an output impedance matching  
input (ZQ). Synchronous data outputs are tightly matched to the  
two output echo clocks CQ/CQ, eliminating the need to capture  
data separately from each individual DDR II SIO SRAM in the  
system design. Output data clocks (C/C) enable maximum  
system clocking and data synchronization flexibility.  
Expanded HSTL output voltage (1.4 V to VDD  
)
Supports both 1.5 V and 1.8 V IO supply  
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1 compatible test access port  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Phase locked loop (PLL) for accurate data placement  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum operating frequency  
333 MHz  
333  
300 MHz  
300  
250 MHz Unit  
250  
430  
490  
MHz  
mA  
Maximum operating current  
× 18  
× 36  
490  
460  
600  
Not Offered  
Cypress Semiconductor Corporation  
Document Number: 001-57829 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 4, 2018  

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