Datasheet > CY7C1417AV18-250BZC

CY7C1417AV18-250BZC

更新时间： 2024-02-29 02:27:13

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
28页	467K
描述
DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1417AV18-250BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.6
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	33554432 bit
内存集成电路类型：	DDR SRAM	内存宽度：	8
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.25 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.7 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

CY7C1417AV18-250BZC 数据手册

浏览型号CY7C1417AV18-250BZC的Datasheet PDF文件第2页

浏览型号CY7C1417AV18-250BZC的Datasheet PDF文件第3页

浏览型号CY7C1417AV18-250BZC的Datasheet PDF文件第4页

浏览型号CY7C1417AV18-250BZC的Datasheet PDF文件第5页

浏览型号CY7C1417AV18-250BZC的Datasheet PDF文件第6页

CY7C1417AV18

CY7C1428AV18

CY7C1419AV18

CY7C1421AV18

36-Mbit DDR-II SRAM 4-Word Burst

Architecture

Features

Functional Description

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

• 300-MHz clock for high bandwidth

The CY7C1417AV18, CY7C1428AV18, CY7C1419AV18 and

CY7C1421AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II (Double Data Rate) architecture. The

DDR-II consists of an SRAM core with advanced synchronous

peripheral circuitry and a two-bit burst counter. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with four 8-bit

words in the case of CY7C1417AV18 and four 9-bit words in

the case of CY7C1428AV18 that burst sequentially into or out

of the device. The burst counter always starts with “00” inter-

nally in the case of CY7C1417AV18 and CY7C1428AV18. On

CY7C1419AV18 and CY7C1421AV18, the burst counter takes

in the last two significant bits of the external address and

bursts four 18-bit words in the case of CY7C1419AV18, and

four 36-bit words in the case of CY7C1421AV18, sequentially

into or out of the device.

• 4-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SRAM

in the system design. Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

CY7C1417AV18 – 4M x 8

CY7C1428AV18 – 4M x 9

CY7C1419AV18 – 2M x 18

CY7C1421AV18 – 1M x 36

Selection Guide

300 MHz

300

278 MHz

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

278

775

825

700

600

500

Cypress Semiconductor Corporation

Document Number: 38-05618 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 25, 2006

12 3 4 5 6 7...28

下载PDF

与CY7C1417AV18-250BZC相关器件

型号	品牌	描述	获取价格	数据表
CY7C1417AV18-250BZI	CYPRESS	DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	获取价格
CY7C1417AV18-250BZXI	CYPRESS	DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA	获取价格
CY7C1417AV18-278BZXC	CYPRESS	DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA	获取价格
CY7C1417AV18-300BZC	CYPRESS	DDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	获取价格
CY7C1418AV18	CYPRESS	36-Mbit DDR-II SRAM 2-Word Burst Architecture	获取价格
CY7C1418AV18-167BZC	CYPRESS	36-Mbit DDR-II SRAM 2-Word Burst Architecture	获取价格

与CY7C1417AV18-250BZC相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1417AV18-250BZC

CY7C1417AV18-250BZC 技术参数

CY7C1417AV18-250BZC 数据手册

与CY7C1417AV18-250BZC相关器件

与CY7C1417AV18-250BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1417AV18-250BZC

CY7C1417AV18-250BZC 技术参数

CY7C1417AV18-250BZC 数据手册

与CY7C1417AV18-250BZC相关器件

与CY7C1417AV18-250BZC相关文章

您还可以找

您在本页遇到什么问题？