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CY7C1414KV18-250BZXC PDF预览

CY7C1414KV18-250BZXC

更新时间: 2024-12-01 09:44:31
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赛普拉斯 - CYPRESS 静态存储器
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30页 859K
描述
36-Mbit QDR? II SRAM 2-Word Burst Architecture

CY7C1414KV18-250BZXC 数据手册

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CY7C1410KV18, CY7C1425KV18  
CY7C1412KV18, CY7C1414KV18  
36-Mbit QDR® II SRAM 2-Word  
Burst Architecture  
36-Mbit QDR® II SRAM 2-Word Burst Architecture  
Features  
Configurations  
Separate independent read and write data ports  
Supports concurrent transactions  
CY7C1410KV18 – 4 M × 8  
CY7C1425KV18 – 4 M × 9  
CY7C1412KV18 – 2 M × 18  
CY7C1414KV18 – 1 M × 36  
333 MHz clock for high bandwidth  
2-word burst on all accesses  
Double data rate (DDR) Interfaces on both read and write ports  
(data transferred at 666 MHz) at 333 MHz  
Functional Description  
The CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and  
CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs,  
equipped with QDR II architecture. QDR II architecture consists  
of two separate ports: the read port and the write port to access  
the memory array. The read port has dedicated data outputs to  
support read operations and the write port has dedicated data  
inputs to support write operations. QDR II architecture has  
separate data inputs and data outputs to completely eliminate  
the need to “turnaround” the data bus that exists with common  
I/O devices. Access to each port is through a common address  
bus. Addresses for read and write addresses are latched on  
alternate rising edges of the input (K) clock. Accesses to the  
QDR II read and write ports are completely independent of one  
another. To maximize data throughput, both read and write ports  
are equipped with DDR interfaces. Each address location is  
associated with two 8-bit words (CY7C1410KV18), 9-bit words  
(CY7C1425KV18), 18-bit words (CY7C1412KV18), or 36-bit  
words (CY7C1414KV18) that burst sequentially into or out of the  
device. Because data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K and C  
and C), memory bandwidth is maximized while simplifying  
system design by eliminating bus turnarounds.  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Single multiplexed address input bus latches address inputs  
for both read and write ports  
Separate port selects for depth expansion  
Synchronous internally self-timed writes  
QDR® II operates with 1.5 cycle read latency when DOFF is  
asserted HIGH  
OperatessimilartoQDRIdevicewith1cyclereadlatencywhen  
DOFF is asserted LOW  
Available in × 8, × 9, × 18, and × 36 configurations  
Full data coherency, providing most current data  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD  
Supports both 1.5 V and 1.8 V I/O supply  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Available in 165-ball FBGA package (13 × 15 ×1.4 mm)  
Offered in both Pb-free and non Pb-free Packages  
Variable drive HSTL output buffers  
JTAG 1149.1 compatible test access port  
Phase locked loop (PLL) for accurate data placement  
Table 1. Selection Guide  
Description  
Maximum operating frequency  
Maximum operating current  
333 MHz  
333  
300 MHz  
300  
250 MHz  
250  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
× 8  
× 9  
730  
680  
590  
510  
450  
730  
680  
590  
510  
450  
× 18  
× 36  
750  
700  
610  
520  
460  
910  
850  
730  
620  
540  
Cypress Semiconductor Corporation  
Document Number: 001-57825 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 27, 2011  
[+] Feedback  

CY7C1414KV18-250BZXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1414KV18-250BZI CYPRESS

类似代替

36-Mbit QDR® II SRAM Two-Word Burst Architec
CY7C1414KV18-250BZC CYPRESS

类似代替

36-Mbit QDR? II SRAM 2-Word Burst Architecture

与CY7C1414KV18-250BZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1414KV18-250BZXCT CYPRESS

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Standard SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216
CY7C1414KV18-250BZXCT INFINEON

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Synchronous SRAM
CY7C1414KV18-250BZXI CYPRESS

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36-Mbit QDR® II SRAM Two-Word Burst Architec
CY7C1414KV18-250BZXIT CYPRESS

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暂无描述
CY7C1414KV18-300BZC CYPRESS

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36-Mbit QDR® II SRAM Two-Word Burst Architec
CY7C1414KV18-300BZI CYPRESS

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36-Mbit QDR® II SRAM Two-Word Burst Architec
CY7C1414KV18-300BZXC CYPRESS

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36-Mbit QDR? II SRAM 2-Word Burst Architecture
CY7C1414KV18-300BZXI CYPRESS

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36-Mbit QDR® II SRAM Two-Word Burst Architec
CY7C1414KV18-300BZXI INFINEON

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Synchronous SRAM
CY7C1414KV18-333BZC CYPRESS

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36-Mbit QDR? II SRAM 2-Word Burst Architecture