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CY7C1414BV18-250BZI PDF预览

CY7C1414BV18-250BZI

更新时间: 2024-12-01 06:51:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
28页 651K
描述
36-Mbit QDR-II SRAM 2-Word Burst Architecture

CY7C1414BV18-250BZI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.34
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):250 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:17 mm内存密度:37748736 bit
内存集成电路类型:QDR SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:165字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):220电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.475 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:1 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm
Base Number Matches:1

CY7C1414BV18-250BZI 数据手册

 浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第2页浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第3页浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第4页浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第5页浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第6页浏览型号CY7C1414BV18-250BZI的Datasheet PDF文件第7页 
CY7C1410BV18, CY7C1425BV18  
CY7C1412BV18, CY7C1414BV18  
36-Mbit QDR™-II SRAM 2-Word  
Burst Architecture  
Features  
Configurations  
Separate independent read and write data ports  
Supports concurrent transactions  
CY7C1410BV18 – 4M x 8  
CY7C1425BV18 – 4M x 9  
CY7C1412BV18 – 2M x 18  
CY7C1414BV18 – 1M x 36  
250 MHz clock for high bandwidth  
2-word burst on all accesses  
Functional Description  
DoubleDataRate(DDR)interfacesonbothreadandwriteports  
(data transferred at 500 MHz) at 250 MHz  
The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18, and  
CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs,  
equipped with QDR-II architecture. QDR-II architecture consists  
of two separate ports: the read port and the write port to access  
the memory array. The read port has data outputs to support read  
operations and the write port has data inputs to support write  
operations. QDR-II architecture has separate data inputs and  
data outputs to completely eliminate the need to “turn-around”  
the data bus required with common IO devices. Access to each  
port is accomplished through a common address bus. The read  
address is latched on the rising edge of the K clock and the write  
address is latched on the rising edge of the K clock. Accesses to  
the QDR-II read and write ports are completely independent of  
one another. To maximize data throughput, both read and write  
ports are provided with DDR interfaces. Each address location  
is associated with two 8-bit words (CY7C1410BV18), 9-bit words  
(CY7C1425BV18), 18-bit words (CY7C1412BV18), or 36-bit  
words (CY7C1414BV18) that burst sequentially into or out of the  
device. Because data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K and C  
and C), memory bandwidth is maximized while simplifying  
system design by eliminating bus “turn-arounds.”  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high-speed  
systems  
Single multiplexed address input bus latches address inputs  
for both read and write ports  
Separate port selects for depth expansion  
Synchronous internally self-timed writes  
QDR™-IIoperateswith1.5cyclereadlatencywhenDelayLock  
Loop (DLL) is enabled  
Operates as a QDR-I device with 1 cycle read latency in DLL  
off mode  
Available in x 8, x 9, x 18, and x 36 configurations  
Full data coherency, providing most current data  
Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD  
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
Variable drive HSTL output buffers  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
JTAG 1149.1 compatible test access port  
Delay Lock Loop (DLL) for accurate data placement  
Selection Guide  
Description  
250 MHz  
250  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
x8  
x9  
800  
700  
620  
800  
700  
620  
x18  
x36  
850  
725  
650  
1000  
850  
740  
Cypress Semiconductor Corporation  
Document #: 001-07036 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 16, 2008  
[+] Feedback  

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